Computer Organization & Architecture
50 articles in this topic
Set Associative Mapping: Address Split, LRU Trace and a 4-Way Cache Worked Example
Build set associative mapping from cache lines and sets, then decode 0x2B6D4, trace true LRU in one 4-way set, compare AMAT, and correct common numerical traps.
Updated 17 Sep 20266 min readComputer Organization & Architecture
Instruction Formats and Addressing Modes for GATE: One Cross-Concept COA Problem Solved
Decode one teaching instruction from 0x2E35FFEC, calculate its effective address, read the little-endian value, and trace the result through a five-stage pipeline.
Updated 15 Sep 20266 min readComputer Organization & Architecture
Memory Organisation and Performance: Cache Mapping, AMAT and Worked GATE Examples
Connect cache capacity, address fields and access time through one 32-bit worked system. Then compare mapping choices and solve a past GATE-style field relation.
Updated 14 Sep 20265 min readComputer Organization & Architecture
Instruction Types in Computer Organization: Concepts, Worked Trace and GATE Question Patterns
Classify instructions by the state they change, then trace a toy CPU across registers, flags, memory, a branch, an output port, and the program counter.
Updated 12 Sep 20266 min readComputer Organization & Architecture
Floating-Point Basics: Binary Normalisation, Worked Examples and Exam Patterns
Connect sign, significand, exponent and bias through one continuous toy-format example. Then see exactly why 0.1 needs rounding and how spacing changes with scale.
Updated 11 Sep 20265 min readComputer Organization & Architecture
Disk Access Time and Performance: Formulas, Worked Example and GATE Traps
Learn how seek time, rotational latency and transfer time combine, then apply the formulas to random and contiguous reads without losing track of units.
Updated 10 Sep 20265 min read59 viewsComputer Organization & Architecture
Direct Memory Access (DMA) Explained: Bus Cycles, Transfer Modes and a Worked Example
DMA becomes easier when you trace bus ownership, addresses and timing as one transfer. This guide follows a 6 KiB block through burst, cycle-stealing and transparent modes.
Updated 8 Sep 20266 min readComputer Organization & Architecture
Booth’s Algorithm Explained: Signed Binary Multiplication, Full Trace and Exam Traps
Learn how Booth’s Algorithm reads bit pairs, updates fixed-width registers, and shifts them as one field. A four-cycle trace proves why 0011 × 1011 gives -15.
Updated 7 Sep 20266 min read66 viewsComputer Organization & Architecture
Input and Output Devices in COA: Interfaces, Interrupts and DMA with a Worked Example
Input and output devices in COA explained through interfaces, polling, interrupts and DMA, plus a FIFO that fills in 640 microseconds and loses 6 bytes at 700 microseconds.
Updated 5 Sep 20267 min readComputer Organization & Architecture
Computer Architecture Evolution and History: From Stored Programs to Multicore Systems
Follow the causal path from physical reconfiguration to stored programs, integrated processors, memory hierarchy and multicore, with checked numerical examples.
Updated 4 Sep 20265 min readComputer Organization & Architecture
Character Encoding Schemes: ASCII, ISCII, Unicode and UTF-8 Worked Examples
Trace Aह😀 from code points to UTF-8, UTF-16BE and UTF-32BE. Then decode bytes, compare storage and correct the most common encoding mistakes.
Updated 2 Sep 20265 min read56 viewsComputer Organization & Architecture
CPU Organization Basics: Registers, Instruction Cycle and Worked Examples
Follow PC, MAR, MDR, IR and AC through LOAD, ADD and STORE on a small 16-bit CPU. Then calculate opcode space, address capacity and common trace traps.
Updated 31 Aug 20265 min readComputer Organization & Architecture