Instruction Structure in Computer Organization: Fields, Encoding and Exam Problems

An instruction word looks like an arbitrary row of bits until every field is tied to a CPU decision. That is why learners may remember a format but still get stuck when the widths change. Read field boundaries, calculate encoding capacity and check an answer without memorising one architecture. The same habit carries across other GATE Computer Organization topics.

Start with the job of an instruction structure

An instruction is an encoded command that tells a processor what to do and where its operands are. An instruction set is the processor's collection of commands and conventions. An instruction format is the bit layout of one instruction.

Four field roles are especially useful:

• The opcode identifies an operation such as add or load.

• An operand or register specifier identifies a source or destination.

• An addressing-mode field says how to interpret an operand.

• An immediate or displacement field carries a constant or offset.

A real architecture may combine, omit or reinterpret fields. Fixed-length instructions make boundaries predictable and every bit countable. Variable-length instructions spend extra bits only when needed.

Start every such problem with two checks. All field widths must add to the full instruction width. A field of k bits can represent at most 2^k distinct bit patterns.

Address count changes which operands are explicit

Address count describes how many operand locations an instruction names. It does not determine the total word width, because opcode and operand fields still share the machine's bit budget.

The earlier Instruction Formats and Addressing Modes in COA: Complete Guide with Worked Examples owns the full one-expression translation and six-mode effective-address survey. This post uses only a compact address-form table before concentrating on bit-by-bit 16-bit decoding and a complete opcode-space conservation proof.

Decode a 16-bit instruction field by field

Consider this fixed toy format:

The widths total 4 + 2 + 3 + 7 = 16. Their capacities are 2^4 = 16 opcodes, 2^2 = 4 modes, 2^3 = 8 registers and 2^7 = 128 displacements. Because the displacement is unsigned, its values run from 0 through 127.

Now decode 0101 10 011 1111010:

• 0101 means LOAD in this toy ISA.

• Mode 10 means base-relative addressing.

• 011 selects R3.

• 1111010 is 64 + 32 + 16 + 8 + 2 = 122, which is 0x7A.

Given R3 = 0x1200, the effective address is:

0x1200 + 0x007A = 0x127A

If M[0x127A] = 0x003C, the instruction loads 0x003C, which is decimal 60. The opcode table and mode meanings belong only to this example. Computer Instruction Explained: Format, Instruction Cycle and a 16-Bit Worked Example continues from field decoding through PC movement and write-back; this example stops at the bit boundaries and effective address. For binary-to-hex conversion, review Number Systems and Base Conversions.

Solve an expanding-opcode allocation problem

A 16-bit three-address instruction has three 4-bit register fields. They occupy 3 x 4 = 12 bits, leaving 16 - 12 = 4 opcode bits and 16 top-level prefixes.

Reserve prefixes 0000 through 0111 for 8 three-address operations. That leaves prefixes 1000 through 1111, also 8 prefixes, for another format.

A two-address format needs two 4-bit register fields. Removing the third field frees 4 extension bits. Each unused prefix expands into 2^4 = 16 opcodes. The maximum is:

8 x 2^4 = 8 x 16 = 128

The tempting answer 2^8 = 256 wrongly treats all 16 top-level prefixes as available. Half were already assigned.

Count complete 16-bit patterns to verify the allocation:

• Three-address patterns: 8 x 2^12 = 8 x 4,096 = 32,768.

• Two-address patterns: 128 x 2^8 = 128 x 256 = 32,768.

• Total: 32,768 + 32,768 = 65,536 = 2^16.

Recognise the main exam-style question patterns

Instruction-structure problems usually belong to five families:

1. Calculate field widths from required counts.

2. Calculate available counts from given widths.

3. Decode a given bit string.

4. Allocate expanding opcodes among formats.

5. Translate an expression into zero-, one-, two- or three-address instructions.

Use the same solving order each time. Draw the word, write known widths, convert each required count N into ceil(log2 N) bits, subtract from the total, then interpret the remainder. A 12-bit address field has 2^12 = 4,096 patterns, representing addresses 0 through 4,095. Only then apply any stated addressing rule.

Begin with direct field-width questions before mixing decoding, signed values and opcode allocation.

Avoid traps that make correct arithmetic look wrong

Separate the number of values from the largest unsigned value. Seven bits provide 128 patterns, but the largest unsigned value is 127. Fifty registers require ceil(log2 50) = 6 bits because 2^5 = 32 is too small and 2^6 = 64 is sufficient.

Do not assume a signed displacement, byte addressing, alignment or opcode meaning unless the question provides it. In the earlier example, the 7-bit displacement was explicitly unsigned. If 1111010 were signed 7-bit two's complement, its value would be 122 - 128 = -6, and the effective address would be 0x1200 - 0x0006 = 0x11FA, not 0x127A.

Finish with a three-part self-check:

1. Do the field widths total 16?

2. Does each chosen value fit its field?

3. Does replaying the dataflow produce the requested result?

The short version, then practise in the right order

Fields divide an instruction word into CPU decisions, and their widths limit the encodings. Address-count forms change where operands live. Expanding opcodes reuse prefixes available from another format.

Practise in increasing order: direct width calculations, bit-string decoding, address-form comparison and finally expanding opcodes. GATE-focused learners can continue with GATE Guidance by Sanchit Sir. Work from the boundaries first, and the bit string stops looking arbitrary.