Data Hazards and Solutions MCQs: 12 Solved Questions with Explanations

Data-hazard questions mix dependency naming, forwarding, renaming and pipeline timing; a slow stage can wreck a correct RAW call.

Try all 12 before reading each answer; for a refresher, read Pipelining in Computer Architecture Explained.

1. Data hazards quick reference: RAW, WAR, WAW and the real pipeline hazard

Take I1: ADD R1,R2,R3, I2: SUB R4,R1,R5, I3: MUL R2,R6,R7, I4: DIV R1,R8,R9. In a simple in-order pipeline only RAW ordinarily creates the hazard. RAW: I1 to I2 on R1. WAR: I1 to I3 on R2, I2 to I4 on R1. WAW: I1 to I4 on R1. Thus RAW = 1, WAR = 2, WAW = 1; dependencies are not automatically stalls.

2. Data dependency MCQs: identify and count RAW, WAR and WAW

List each instruction's read and write sets first.

Q1. Register dependency that causes a data hazard (GATE 2026, Set 1)

Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?

• (A) Read-after-read

• (B) Read-after-write

• (C) Write-after-read

• (D) Write-after-write

Answer: (B), Read-after-write. The later read needs a result not yet written, so the pipeline forwards or stalls. RAR changes no value; WAR and WAW are name dependencies.

Q2. Output dependency (ISRO 2020)

One instruction tries to write an operand before a previous instruction writes it. This dependency is called

• (A) True dependency

• (B) Anti-dependency

• (C) Output dependency

• (D) Control hazard

Answer: (C), Output dependency. Two writes to one destination create WAW; order must be preserved.

Q3. Dependencies across four instructions (GATE 2024, Set 2, MSQ)

An instruction format has the following structure: Instruction Number: Opcode destination reg, source reg-1, source reg-2 Consider the following sequence of instructions to be executed in a pipelined processor: I1: DIV R3, R1, R2 I2: SUB R5, R3, R4 I3: ADD R3, R5, R6 I4: MUL R7, R3, R8 Which of the following statements is/are TRUE?

• (A) There is a RAW dependency on R3 between I1 and I2

• (B) There is a WAR dependency on R3 between I1 and I3

• (C) There is a RAW dependency on R3 between I2 and I3

• (D) There is a WAW dependency on R3 between I3 and I4

Answer: (A) only. I1 to I2 is RAW on R3. B is really WAW on R3, C is RAW on R5, and D is really RAW.

Q4. Count two RAW dependencies (NAT practice question)

Given I0: DIV R2,R0,R1, I1: MUL R5,R1,R4 and I2: SUB R3,R5,R2, how many RAW dependencies are there?

Answer: 2. I0 to I2 on R2 and I1 to I2 on R5; R1 is only read.

3. Forwarding, bypassing and register-renaming MCQs

Forwarding bypasses write-back when a result is ready; a stall covers the rest. Renaming removes WAR and WAW, never RAW.

Q5. What forwarding can and cannot do (GATE 2024, Set 1, MSQ)

For a five-stage IF, ID, EX, MEM and WB pipeline, which forwarding statements are correct?

• (A) In a pipelined execution, forwarding means the result from a source stage of an earlier instruction is passed on to the destination stage of a later instruction

• (B) In forwarding, data from the output of the MEM stage can be passed on to the input of the EX stage of the next instruction

• (C) Forwarding cannot prevent all pipeline stalls

• (D) Forwarding does not require any extra hardware to retrieve the data from the pipeline stages

Answer: (A) and (C). A defines forwarding. A load-use result can arrive too late, so C holds and B fails for the next instruction. D is false: bypass paths are extra hardware.

Q6. Limits of bypassing and branch prediction (GATE 2008)

Which statements are NOT true? I. Bypassing handles all RAW hazards. II. Renaming eliminates all register-carried WAR hazards. III. Dynamic branch prediction eliminates control-hazard penalties.

• (A) I and II only

• (B) I and III only

• (C) II and III only

• (D) I, II and III

Answer: (B), I and III only. Load-use RAW can still need a bubble; renaming removes register-carried WAR; misprediction still costs cycles.

Q7. Why a pipeline renames registers (TPSC 2025, Senior Informatics Officer)

Register renaming is done in pipelined processors

• (A) as an alternative to register allocation at compile time

• (B) for efficient access to function parameters and local variables

• (C) to handle certain kinds of hazards

• (D) as part of address translation

Answer: (C). Physical registers remove WAR and WAW name conflicts, never RAW.

4. Pipeline timing MCQs: forwarding with multi-cycle execution

Count fill-and-drain time first, then extra multi-cycle stage occupation; never double-count a blocked cycle.

Q8. Three dependent instructions with a 3-cycle MUL (GATE 2007)

Consider a pipelined processor with the following four stages: IF: Instruction Fetch ID: Instruction Decode and Operand Fetch EX: Execute WB: Write Back The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction needs 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions? ADD R2, R1, R0 R2 <- R0 + R1 MUL R4, R3, R2 R4 <- R3 \* R2 SUB R6, R5, R4 R6 <- R5 - R4

• (A) 7

• (B) 8

• (C) 10

• (D) 14

Answer: (B), 8 cycles. Baseline: (3+4-1=6). MUL adds (3-1=2) EX cycles. Total: (6+2=8). Forwarding adds no write-back wait.

Q9. Five-stage pipeline with MUL and DIV (GATE 2010)

A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? $\begin{array} c{} \textbf {Instruction} & \textbf{Meaning of instruction} \\ \text{$I _0$: MUL $R _2$,$R _0$,$R _1$} & \text{R}_2 \gets \text{R}_0*\text{R}_1\\ \text{$I _1$: DIV $R _5,R _3,R _4$} & \text{R}_5 \gets \text{R}_3 ∕ \text{R}_4\\ \text{$I _2$: ADD $R _2,R _5,R _2$} & \text{R}_2 \gets \text{R}_5 + \text{R}_2 \\ I_3: \text{SUB} \:\text{R}_5,\text{R}_2,\text{R}_6 & \text{R}_5 \gets \text{R}_2 - \text{R}_6 \\\end{array}$

• (A) 13

• (B) 15

• (C) 17

• (D) 19

Answer: (B), 15 cycles. Baseline: (4+5-1=8). Extra PO time: ((3-1)+(6-1)=7). Total: (8+7=15). Forwarding adds no separate wait.

Q10. Four-stage pipeline with variable PO latency (GATE 2015, Set 2, NAT)

Consider the sequence of machine instructions given below: MUL R5, R0, R1 DIV R6, R2, R3 ADD R7, R5, R6 SUB R8, R7, R4 In the above sequence, R0 to R8 are general purpose registers. In the instructions shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages: (1) Instruction Fetch and Decode (IF), (2) Operand Fetch (OF), (3) Perform Operation (PO) and (4) Write back the result (WB). The IF, OF and WB stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD or SUB instruction, 3 clock cycles for MUL instruction and 5 clock cycles for DIV instruction. The pipelined processor uses operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instructions is ___________.

Answer: 13. Baseline: (4+4-1=7). MUL adds (3-1=2), and DIV adds (5-1=4). Total: (7+2+4=13). ADD's wait overlaps occupied PO time.

5. Anti-dependence and longer RAW-chain MCQs

Q11. Anti-dependence between instruction pairs (GATE 2015, Set 3)

Consider the following code sequence having five instructions 𝐼 1 to 𝐼 5 . Each of these instructions has the following format. OP Ri, Rj, Rk where operation OP is performed on contents of registers Rj and Rk and the result is stored in register Ri. 𝐼 1 : ADD R1, R2, R3 𝐼 2 : MUL R7, R1, R3 𝐼 3 : SUB R4, R1, R5 𝐼 4 : ADD R3, R2, R4 𝐼 5 : MUL R7, R8, R9 Consider the following three statements. S1: There is an anti-dependence between instructions 𝐼 2 and 𝐼 5 S2: There is an anti-dependence between instructions 𝐼 2 and 𝐼 4 S3: Within an instruction pipeline an anti-dependence always creates one or more stalls Which one of above statements is/are correct?

• (A) Only S1 is true

• (B) Only S2 is true

• (C) Only S1 and S3 are true

• (D) Only S2 and S3 are true

Answer: (B), only S2 is true. I2 reads R3 before I4 writes it (WAR). I2 and I5 are WAW on R7, and anti-dependence need not stall an in-order pipeline.

Q12. Count a three-edge RAW chain (NAT practice question)

For I0: DIV R2,R0,R1, I1: MUL R5,R1,R4, I2: SUB R3,R5,R2 and I3: ADD R5,R3,R6, how many RAW dependencies are there?

Answer: 3. I0 to I2 on R2, I1 to I2 on R5 and I2 to I3 on R3; I1 and I3 are only WAW on R5.

6. How exams test data hazards and where students lose marks

Read destination-first formats correctly; Addressing Modes and Instruction Formats helps here. Underline destinations, circle sources, then draw forward arrows before any cycle table.

7. Data hazards MCQs: the short version and next step

• RAW carries a produced value to a later read; forwarding reduces but cannot remove every RAW stall.

• Renaming removes WAR and WAW name conflicts; cycle totals are fill-and-drain time plus extra stage occupation, counted once.

For structured Computer Architecture teaching and practice, consider GATE Guidance by Sanchit Sir; broader options sit under GATE CS Exam Preparation.

Now retry Q3, Q5, Q9 and Q11 without looking at the explanations.