Complex and Relative Addressing Modes MCQs: 11 Solved COA Questions with Explanations

Start each calculation with the effective-address rule. Addressing Modes and Instruction Formats MCQs is the broader practice set for basic modes and instruction-format encoding. Multi-term addresses, relocation, segment arithmetic, stack side effects and indirect-memory cycles require a separate trace for every register, pointer and update.

Related reading: instruction formats and addressing and COA addressing mode questions.

1. Build one address-formation sheet before solving

Notation: A is an address or displacement; R, register content; M[x], memory; PC_next, post-fetch PC; EA, effective address.

Follow the stem's rule because textbook names overlap.

2. Indexed, base and displacement MCQs

Q1. Constant added to a register

ISRO 2009. Open the live solved question.

In which addressing mode, the effective address of the operand is generated by adding a constant value to the content of a register?

• (a) Absolute mode

• (b) Indirect mode

• (c) Immediate mode

• (d) Index mode

Answer: (d) Index mode. EA = R + A. For R = 1200 and A = 36, EA = 1200 + 36 = 1236.

Q2. Array access in contiguous memory

Which of the following addressing mode is best suited to accesses elements of an array of contiguous memory location?

• (a) Indexed addressing mode

• (b) Base register addressing mode

• (c) Relative addressing mode

• (d) None of these.

Answer: (a) Indexed addressing mode. For base 4000, width 4, and index 6, EA = 4000 + 6 x 4 = 4000 + 24 = 4024.

Q3. Register indirect plus an offset

UGC NET 2016. Open the live solved question.

The _____ addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction.

• (a) Base indexed

• (b) Base indexed plus displacement

• (c) Indexed

• (d) Displacement

Answer: (d) Displacement. One explicit offset added to one named register gives EA = R + A. For R = 5000 and A = 28, EA = 5028.

Q4. Two registers and a displacement

The effective address of the following instruction is MUL 5(R1,R2).

• (a) 5+R1+R2

• (b) 5+(R1*R2)

• (c) 5+[R1]+[R2]

• (d) 5*([R1]+[R2])

Answer: (c) 5+[R1]+[R2]. With [R1] = 1000 and [R2] = 24, EA = 5 + 1000 + 24 = 1029.

3. PC-relative addressing, relocation and position independence

Q5. The false claim about relative addressing

ISRO 2009. Open the live solved question.

Which of the following statements about relative addressing mode is FALSE?

• (a) It enables reduced instruction size

• (b) It allows indexing of array element with same instruction

• (c) It enables easy relocation of data

• (d) It enables faster address calculation than absolute addressing

Answer: (d) It enables faster address calculation than absolute addressing. Relative addressing adds a displacement. If PC_next = 2000 and displacement is -20, EA = 1980. Move the code by 1000: PC_next = 3000, so EA = 2980. The distance remains -20. Option (b) uses relative addressing in the broader base-plus-displacement sense, where changing the displacement selects another array element; PC-relative terminology is narrower.

Q6. What PC-relative addressing is best for

GATE 1996. Open the live solved question. This question also appears in Addressing Modes and Instruction Formats MCQs, where it checks general mode recognition; here the unchanged displacement is traced across two PC locations to explain position-independent code.

Relative mode of addressing is most relevant to writing

• (a) co-routines

• (b) position-independent code

• (c) shareable code

• (d) interrupt handlers

Answer: (b) position-independent code. PC_next = 4096 plus 32 gives 4128; PC_next = 8192 plus the same displacement gives 8224.

Q7. Remember that the PC has advanced

A Program Counter contains a number 825 and address part of the instruction contains the number 24. The effective address in the relative address mode, when an instruction is read from the memory is

• (a) 849

• (b) 850

• (c) 801

• (d) 802

Answer: (b) 850. Fetch advances 825 to 826, so EA = PC_next + A = 826 + 24 = 850.

4. Segmented real-mode address calculation

Q8. Convert CS:IP into a physical address

ISRO 2011. Open the live solved question.

Find the memory address of the next instruction executed by the microprocessor (8086), when operated in real mode for CS=1000 and IP=E000

• (a) 10E00

• (b) 1E000

• (c) F000

• (d) 1000E

Answer: (b) 1E000. 1000H x 10H = 10000H, then 10000H + E000H = 1E000H.

5. Auto-decrement and stack effects

Q9. Pop two stack values, add and push once

GATE 2008. Open the live solved question.

Assume that EA = (X)+ is the effective address equal to the contents of location X, with X incremented by one word length after the effective address is calculated; EA = −(X) is the effective address equal to the contents of location X, with X decremented by one word length before the effective address is calculated; EA = (X)− is the effective address equal to the contents of location X, with X decremented by one word length after the effective address is calculated. The format of the instruction is (opcode, source, destination), which means (destination ← source op destination). Using X as a stack pointer, which of the following instructions can pop the top two elements from the stack, perform the addition operation and push the result back to the stack.

• (a) ADD (X)−, (X)

• (b) ADD (X), (X)−

• (c) ADD −(X), (X)+

• (d) ADD −(X), (X)

Answer: (a) ADD (X)−, (X). With word length 4, start at X = 1000, M[1000] = 9, and M[996] = 6. Source (X)− reads 9 and sets X = 996; destination (X) reads 6. Store 9 + 6 = 15 at M[996]. Final X = 996 points to the result.

6. Mixed modes and execution-cycle memory references

Q10. Match four modes to four effective addresses

An instruction is stored at location 1200 with its address field at location 1201. The address field has the value 600. A processor register R1 contains the number 800. Match the addressing mode (List-I) given below with effective address(EA) (List-II) for the given instruction: List-I List-II i. Direct a. 1400 ii. Relative b. 800 iii. Indexed, with R1 as the index register c. 600 iv. Register Indirect d. 1802

• (a) i-c, ii-d, iii-a, iv-b

• (b) i-c, ii-a, iii-d, iv-b

• (c) i-d, ii-c, iii-b, iv-a

• (d) i-c, ii-d, iii-b, iv-a

Answer: (a) i-c, ii-d, iii-a, iv-b. Direct: EA = 600. After 1200 and 1201, PC_next = 1202; relative: 1202 + 600 = 1802; indexed: 800 + 600 = 1400; register indirect: EA = 800.

Q11. Count only execution-cycle memory references

GATE 2005. Open the live solved question. This question also appears in Addressing Modes and Instruction Formats MCQs, where it contributes to a broad mode survey; here the indexed destination, indirect pointer read, source read and write-back are traced as four separate execution cycles.

Consider a three word machine instruction ADD A[R0], @ B The first operand (destination) "A [R0]" uses indexed addressing mode with R0 as the index register. The second operand (source) "@ B" uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand). The number of memory cycles needed during the execution cycle of the instruction is

• (a) 3

• (b) 4

• (c) 5

• (d) 6

Answer: (b) 4. Excluding fetches, let A = 1000, R0 = 20, B = 2000, M[1020] = 7, M[2000] = 3000, and M[3000] = 5.

1. Read destination M[1000 + 20] = M[1020] = 7.

2. Read pointer M[2000] = 3000.

3. Read source M[3000] = 5.

4. Write 7 + 5 = 12 to M[1020].

Total: 1 + 1 + 1 + 1 = 4 memory cycles.

7. Error log, exam use and next step

Use the GATE CS category to revisit other COA fundamentals. GATE Guidance by Sanchit Sir provides a structured revision path, and the GATE Test Series is the next timed check. Redo Q4, Q7, Q9, Q10 and Q11 without looking at the table.