An instruction format has the following structure: Instruction Number: Opcode…
2024
An instruction format has the following structure:
Instruction Number: Opcode destination reg, source reg-1, source reg-2
Consider the following sequence of instructions to be executed in a pipelined processor:
I1: DIV R3, R1, R2
I2: SUB R5, R3, R4
I3: ADD R3, R5, R6
I4: MUL R7, R3, R8
Which of the following statements is/are TRUE?
- A.
There is a RAW dependency on R3 between I1 and I2
- B.
There is a WAR dependency on R3 between I1 and I3
- C.
There is a RAW dependency on R3 between I2 and I3
- D.
There is a WAW dependency on R3 between I3 and I4
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Correct answer: A
Answer: The statement "There is a RAW dependency on R3 between I1 and I2" is correct. The other provided statements are incorrect.
Key definitions:
Read-after-write (RAW): an earlier instruction writes a register and a later instruction reads that register.
Write-after-read (WAR): an earlier instruction reads a register and a later instruction writes the same register (anti-dependency).
Write-after-write (WAW): two instructions both write the same register; the ordering of writes matters.
Dependencies in the given sequence:
Between I1 (DIV R3, R1, R2) and I2 (SUB R5, R3, R4): RAW on R3, because I1 writes R3 and I2 reads that value.
Between I1 (DIV R3, R1, R2) and I3 (ADD R3, R5, R6): WAW on R3, because both instructions write R3.
Between I2 (SUB R5, R3, R4) and I3 (ADD R3, R5, R6): WAR on R3, because I2 reads R3 before I3 writes a new value.
Between I3 (ADD R3, R5, R6) and I4 (MUL R7, R3, R8): RAW on R3, because I3 writes R3 and I4 reads that value.
Conclusion: Only the statement that there is a RAW dependency on R3 between I1 and I2 is true; the other statements misidentify the dependency types.
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