Structural and Control Hazards MCQs: 12 Solved Pipeline Questions with Explanations

A resource collision is a structural hazard. Uncertainty about the next program counter is a control hazard. Both become numerical when stalls change CPI or flushed instructions change cycle count. Attempt each MCQ, MSQ or NAT before reading its explanation. For weighted penalties, use effective CPI = base CPI + weighted stall cycles. For timing questions, mark fetch, branch resolution, flush, target fetch and pipeline drain. Linked headings open the corresponding question page. For unlinked headings, use the Structural & Control Hazards PYQ Questions hub.

Pipeline hazard types: identify the conflict before calculating

Q1. Pipeline-hazard taxonomy (CDAC CCAT 2025)

Which of the following is NOT a type of pipeline hazard?

• A. Structural

• B. Data

• C. Control

• D. Logical

Answer: D. Logical. The standard classes are structural, data, and control. “Logical hazard” is not one.

Q2. One example of every hazard (ISRO Computer Science, December 2017)

For a pipelines CPU with a single ALU, consider the following:

A. The j + 1st instruction uses the result of jth instruction as an operand

B. Conditional jump instruction

C. jth and j + 1st instructions require ALU at the same time

Which one of the above causes a hazard?

• A. A and B only

• B. B and C only

• C. B only

• D. A , B and C

Answer: D. A, B and C. A is a RAW dependency, B is a control hazard, and C is a single-ALU structural conflict.

Q3. Why pipeline performance suffers (GATE 2002)

The performance of a pipelined processor suffers if :

• A. the pipeline stages have different delays

• B. consecutive instructions are dependent on each other

• C. the pipeline stages share hardware resources

• D. all of the above

Answer: D. All of the above. The slowest stage fixes the clock; dependencies and shared hardware cause stalls. All reduce performance.

Structural and control stalls in effective CPI

For every hazard class h, add frequency(h) × penalty(h) to the ideal CPI. Keep percentages as decimals until the final result.

Q4. Mixed structural, data, and control penalties

A system employs 6 stage instruction pipeline in which 25% instruction result in data dependency, 20% instruction results in control dependency and 5% instruction results in structural dependency. If the penalty for structural dependency is 3 clock, penalty for data dependency is 2 clock and 1 clock for control dependency. then average cycles per instruction are __________.

Answer: 1.85 cycles/instruction.

CPI = 1 + (0.25 × 2) + (0.20 × 1) + (0.05 × 3)

= 1 + 0.50 + 0.20 + 0.15 = 1.85

The control-hazard contribution is 0.20; the structural-hazard contribution is 0.15.

Q5. Speedup after data and control stalls (GATE 2024, Computer Science Set 2)

A non-pipelined instruction execution unit operating at 2 GHz takes an average of 6 cycles to execute an instruction of a program P. The unit is then redesigned to operate on a 5-stage pipeline at 2 GHz. Assume that the ideal throughput of the pipelined unit is 1 instruction per cycle. In the execution of program P, 20% instructions incur an average of 2 cycles stall due to data hazards and 20% instructions incur an average of 3 cycles stall due to control hazards. The speedup (rounded off to one decimal place) obtained by the pipelined design over the non-pipelined design is _________

Answer: 3.0. Pipeline CPI is 1 + (0.20 × 2) + (0.20 × 3) = 2.0. Equal clocks give speedup 6/2 = 3.0.

Control-hazard timing: branch resolution, flush, and drain

Count wrong-path or idle fetches until the target is available. After the last useful fetch, add the remaining drain stages.

Q6. Taken branch in a five-stage pipeline (GATE 2013)

Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions I₁, I₂, I₃, …, I₁₂ is executed in this pipelined processor. Instruction I₄ is the only branch instruction and its branch target is I₉. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is

• A. 132

• B. 165

• C. 176

• D. 328

Answer: B. 165 ns. Clock period is max(5, 7, 10, 8, 6) + 1 = 11 ns. I₄ is FI4 and EI7, so flush I₅ to I₇; fetch I₉ to I₁₂ in cycles 8 to 11, reaching WO15. Thus 15 × 11 = 165 ns. Check: 4 useful + 3 flushed + 4 target fetches + 4 drain cycles = 15.

Q7. Total time from a repeated branch penalty (GATE 2006)

A CPU has a five-stage pipeline and runs at 1 GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction

computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new instructions following a conditional branch until the branch outcome is known. A program executes 10⁹ instructions out of which 20% are conditional branches. If each instruction takes one cycle to complete on average, the total execution time of the program is:

• A. 1.0 second

• B. 1.2 seconds

• C. 1.4 seconds

• D. 1.6 seconds

Answer: C. 1.4 seconds. The 0.20 × 10⁹ = 2 × 10⁸ branches add 4 × 10⁸ stopped-fetch cycles. Time is (10⁹ + 4 × 10⁸)/(10⁹ cycles/second) = 1.4 seconds.

Q8. Unconditional jump to I₉₈

Consider a 4-stage instruction pipeline with stages IF (Instruction Fetch), ID (Instruction Decode), EX (Execute) and MO (Memory Operation), where each stage takes 9 ns. A program having 100 instructions I₁, I₂, I₃, ....., I₁₀₀ is executed in this pipelined processor. Instruction I₄ is the unconditional jump instruction, and the branch address is known only after the EX stage. The time needed to complete the execution of the program if the branch target address is the 98th instruction is ______ (in ns).

Answer: 108 ns. I₄ is IF4, ID5, EX6; flush I₅ and I₆, then fetch I₉₈ to I₁₀₀ in cycles 7 to 9. I₁₀₀ reaches MO12, so 12 × 9 = 108 ns. Check: 4 + 7 - 1 = 10 ideal cycles, plus two flushed slots.

Branch prediction: convert accuracy into saved CPI

Q9. Hazard mitigated by branch prediction (CDAC CCAT 2025)

Branch prediction is used primarily to mitigate:

• A. Data hazards

• B. Control hazards

• C. Structural hazards

• D. Cache misses

Answer: B. Control hazards. A branch makes the next program counter uncertain. Prediction keeps fetch moving during resolution.

Q10. Speedup from an 80% accurate predictor (GATE 2022)

A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor X2 operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for X1 and X2. If the BPU has a prediction accuracy of 80%, the speed up (rounded off to two decimal places) obtained by X2 over X1 in executing P is____________.

Answer: 1.43. CPI_X1 = 1 + 0.30 × 2 = 1.60. Misprediction is 0.20, so CPI_X2 = 1 + 0.30 × 0.20 × 2 = 1.12. Equal clocks give 1.60/1.12 = 1.42857..., or 1.43.

Delayed branching: know what the delay slot guarantees

A branch delay slot is the position immediately after a branch in memory. It executes on either outcome, so only work safe on both paths belongs there.

Q11. Meaning of a delayed conditional branch (GATE 2008)

Delayed branching can help in the handling of control hazards. For all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or false,

• A. the instruction following the conditional branch instruction in memory is executed

• B. the first instruction in the fall through path is executed

• C. the first instruction in the taken path is executed

• D. the branch takes longer to execute than any other instruction

Answer: A. The next instruction occupies the delay slot and executes for either outcome. Useful work there hides control-hazard latency.

Predict taken versus predict not taken: compare both CPIs

Q12. Static branch-prediction choice

Assume an instruction mix of 20% conditional branches, 5% unconditional branches, 75% all others. 65% of the conditional branches are taken. We have a 5-stage pipeline where branch target locations are computed in the 2nd stage and branch conditions in the 4th stage. Assume no other sources of pipeline stalls. We want to decide whether to implement "predict taken" or "predict not taken" for branch prediction for this machine. For "predict not taken", even unconditional branches are assumed not taken. Which of the following is correct?

• A. "predict taken" is better for this machine.

• B. "predict not taken" is better for this machine.

• C. For "predict taken" branch predictions, CPI is the 1.54

• D. For "predict not taken" branch predictions, CPI is the 1.54

Answer: A and D. Predict-taken penalty is (0.20 × 0.65 × 1) + (0.20 × 0.35 × 3) + (0.05 × 1) = 0.13 + 0.21 + 0.05 = 0.39, giving CPI 1.39. Predict-not-taken penalty is (0.20 × 0.65 × 3) + (0.05 × 3) = 0.39 + 0.15 = 0.54, giving CPI 1.54. Thus A and D are correct.

Structural and control hazards: score map and next step

A score of 10 to 12 means start timed practice. At 7 to 9, redo weighted CPI and cycle traces. At 0 to 6, revisit classification. Questions 1 to 4 address hazard types, questions 5 to 8 address CPI and timing, and questions 9 to 12 address prediction and delayed branching.

Use Pipelining in Computer Architecture Explained for the complete pipeline model. Use Data Hazards and Solutions MCQs for RAW, WAR, WAW, forwarding and register renaming; return to these questions for resource conflicts, branch timing, prediction and delayed branching. GATE Guidance by Sanchit Sir structures the subject, while GATE CS Exam Preparation Courses & Test Series shows broader options.