A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode…

A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions?

$\begin{array} c{} \textbf {Instruction} & \textbf{Meaning of instruction} \\ \text{$I _0$: MUL $R _2$,$R _0$,$R _1$} & \text{R}_2 \gets \text{R}_0*\text{R}_1\\ \text{$I _1$: DIV $R _5,R _3,R _4$} & \text{R}_5 \gets \text{R}_3 ∕ \text{R}_4\\ \text{$I _2$: ADD $R _2,R _5,R _2$} & \text{R}_2 \gets \text{R}_5 + \text{R}_2 \\ I_3: \text{SUB} \:\text{R}_5,\text{R}_2,\text{R}_6 & \text{R}_5 \gets \text{R}_2 - \text{R}_6 \\\end{array}$