A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode…
2010
A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions?
\(\begin{array} c{} \textbf {Instruction} & \textbf{Meaning of instruction} \\ \text{$I _0$: MUL $R _2$,$R _0$,$R _1$} & \text{R}_2 \gets \text{R}_0*\text{R}_1\\ \text{$I _1$: DIV $R _5,R _3,R _4$} & \text{R}_5 \gets \text{R}_3 ∕ \text{R}_4\\ \text{$I _2$: ADD $R _2,R _5,R _2$} & \text{R}_2 \gets \text{R}_5 + \text{R}_2 \\ I_3: \text{SUB} \:\text{R}_5,\text{R}_2,\text{R}_6 & \text{R}_5 \gets \text{R}_2 - \text{R}_6 \\\end{array}\)
- A.
13
- B.
15
- C.
17
- D.
19
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Correct answer: B
Answer: 15 clock cycles.
Key idea: IF, ID, OF and WO take 1 cycle each; PO takes 3 cycles for MUL, 6 cycles for DIV, and 1 cycle for ADD/SUB. Operand forwarding is available, so a producer's result becomes available at the end of its PO and can be forwarded to a consumer's OF in the next cycle. The consumer's OF must not occur earlier than the cycle after the producer's PO finishes.
I0 (MUL R2 ← R0 * R1): IF at cycle 1, ID 2, OF 3, PO 4–6 (3 cycles), WO 7.
I1 (DIV R5 ← R3 ∕ R4): IF 2, ID 3, OF 4, PO 5–10 (6 cycles), WO 11.
I2 (ADD R2 ← R5 + R2) depends on R2 from I0 and R5 from I1. R2 from I0 is ready after I0's PO at end of cycle 6 (so usable in OF at cycle 7); R5 from I1 is ready only after I1's PO at end of cycle 10 (so usable in OF at cycle 11). Therefore I2's OF must be at cycle 11, with ID at 10 and IF at 9. Then I2's PO (ADD) is at 12 and WO at 13.
I3 (SUB R5 ← R2 - R6) depends on R2 from I2. I2's PO finishes at cycle 12, so I3's OF can be at cycle 13 (ID 12, IF 11), then PO at 14 and WO at 15.
Final completion: the last write (I3 WO) finishes at cycle 15, so the sequence requires 15 clock cycles.
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