Consider the sequence of machine instructions given below: MUL R5, R0, R1 DIV…
2015
Consider the sequence of machine instructions given below:
MUL R5, R0, R1
DIV R6, R2, R3
ADD R7, R5, R6
SUB R8, R7, R4
In the above sequence, R0 to R8 are general purpose registers. In the instructions shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages: (1) Instruction Fetch and Decode (IF), (2) Operand Fetch (OF), (3) Perform Operation (PO) and (4) Write back the result (WB). The IF, OF and WB stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD or SUB instruction, 3 clock cycles for MUL instruction and 5 clock cycles for DIV instruction. The pipelined processor uses operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instructions is ___________.
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Correct answer: 13
Stages: IF (1), OF (1), PO (variable), WB (1). PO lengths: MUL=3, DIV=5, ADD=1, SUB=1. Forwarding is from PO → OF, but a consumer’s OF must occur after the producer’s PO has finished (so it can get the value).
Number instructions I1..I4 = {MUL, DIV, ADD, SUB}.
Schedule (cycle numbers):
I1 (MUL R5)
IF:1, OF:2, PO:3–5, WB:6
→ R5 ready at end of cycle 5.I2 (DIV R6)
IF:2, OF:3, PO:4–8, WB:9
→ R6 ready at end of cycle 8.I3 (ADD R7 = R5+R6) needs R5 and R6. Earliest OF for I3 must be after both PO completions → after cycle 8 → OF3 at 9. IF3 can be earlier (IF3=3) but OF stalls until 9. Then PO3:10, WB3:11.
So I3: IF:3, OF:9, PO:10, WB:11. → R7 ready at end of 10.I4 (SUB R8 = R7−R4) needs R7. Earliest OF4 must be after R7 ready (end of cycle 10) → OF4 at 11. IF4 was at 4 but OF stalls until 11. Then PO4:12, WB4:13.
So I4: IF:4, OF:11, PO:12, WB:13.
Final write-back completes at cycle 13 → total 13 cycles.
Final box: 13 clock cycles
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