Instruction Formats and Addressing Modes MCQs: 12 Solved Cross-Concept Questions

Instruction-format questions rarely isolate one definition. A single item may combine the effective-address rule with relocation, memory-reference counts, opcode bits, byte alignment, or the next PC. Use Addressing Modes and Instruction Formats MCQs to repair definition-level recognition, then choose the governing rule before calculating. Direct question pages appear on selected headings, and the mixed-topic practice page holds the remaining practice.

1. Addressing modes by purpose: Questions 1-3

Separate purpose from cost: pointer and loop facilities explain why modes exist, register indirect avoids a full address field, indexed addressing handles arrays, and indirection adds a memory read.

Question 1: why addressing modes exist

Consider the following statements:
S1: Addressing modes give programmers facilities such as pointers and memory counters for loop control.
S2: Addressing modes specify how an instruction's address field is interpreted or modified.
Choose the correct option.

A. Only S1 is true

B. Only S2 is true

C. Both S1 and S2 are true

D. Both S1 and S2 are false

Answer: C.

Both statements describe real roles. Register-indirect and auto-update modes provide pointer-like iteration, while every addressing mode also defines the rule that turns an instruction field into an operand or effective address.

Question 2: avoiding a full memory address

UGC NET 2014

Which addressing mode can reference memory without placing a full memory address in the instruction?

A. Direct addressing

B. Indexed addressing

C. Register addressing

D. Register-indirect addressing

Answer: D.

Register-indirect addressing names a short register field, and that register holds the full effective address. Direct addressing carries the address itself; indexed addressing still needs a displacement, while register addressing does not reference memory.

Question 3: mapping source-code patterns to modes

GATE 2005

Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side.

 1 A[1] = B[J];      a Indirect addressing
 2 while (*A++);     b Indexed, addressing
 3 int temp = *x;    c Autoincrement

A. (1, c), (2, b), (3, a)

B. (1, a), (2, c), (3, b)

C. (1, b), (2, c), (3, a)

D. (1, a), (2, b), (3, c)

Answer: C.

B[J] uses indexed addressing, *A++ dereferences and then increments, and *x uses indirect addressing. The matching is therefore (1, b), (2, c), (3, a).

2. Relocation, indirect cost, and the next PC: Questions 4-6

Based addressing relocates through a base register, PC-relative addressing uses the next PC plus a signed displacement, and indirect addressing reads a pointer before the operand.

Question 4: modes suitable for run-time relocation

GATE 2004

Which addressing modes are suitable for program relocation at run time?
(i) Absolute addressing
(ii) Based addressing
(iii) Relative addressing
(iv) Indirect addressing

A. (i) and (iv)

B. (i) and (ii)

C. (ii) and (iii)

D. (i), (ii) and (iv)

Answer: C.

Changing the base relocates based addresses, while relative offsets survive movement. Absolute locations stay fixed, and indirection alone does not ensure relocation.

Question 5: hardwired speed and indirect-memory cost

UGC NET 2020

Given two statements:
Statement I: A hardwired control unit can be optimized for fast operation.
Statement II: Indirect addressing needs two memory references to fetch the operand.
Choose the correct option.

A. Both statements are true

B. Both statements are false

C. Statement I is true, but Statement II is false

D. Statement I is false, but Statement II is true

Answer: A.

Dedicated hardwired logic can be optimized for short control paths. In memory-indirect addressing, one read obtains the effective address and a second read fetches the operand, so both statements are true.

Question 6: PC-relative effective address

A 4-byte instruction is stored in memory at address 1000. The address field of the instruction is at location 1002. The operand used during the execution of the instruction is stored at location X. Choose the correct expression to find X if PC relative addressing mode is used.

(For ex: M [10] represents accessing the value at memory location 10).

A. X = 1000 + M[1002]

B. X = 1002 + M[1004]

C. X = 1004 + M[1002]

D. X = 1000 + M[1004]

Answer: C.

The next PC is 1000 + 4 = 1004, and location 1002 supplies M[1002]. Hence X = 1004 + M[1002]; the traps use current PC 1000 or read displacement from 1004.

3. Memory references and address-field meaning: Questions 7-8

Count fetches first: registers add no read, absolute adds one, and indirect adds two.

Question 7: counting memory accesses across three instructions

How many memory accesses are required by the following instructions, written as opcode, destination register, source register 1, and source register 2?

ADD r1, r2, r3
MUL r1, r2, (r3)
DIV r1, r2, @ (r4)

Here (r3) represent absolute addressing mode.

And @(r4) represent indirect addressing mode. Suppose every instruction is one word long, as well as every address.

A. 4

B. 5

C. 6

D. 8

Answer: C.

ADD costs 1 instruction fetch. MUL costs 1 fetch + 1 absolute operand read = 2, and DIV costs 1 fetch + 1 pointer read + 1 operand read = 3, giving 1 + 2 + 3 = 6.

Question 8: what a three-address field can specify

GATE 2015

In a three-address instruction format, what can each explicit address field specify?
S1: A memory operand
S2: A processor register
S3: An implied accumulator register

A. Either S1 or S2

B. Either S2 or S3

C. Only S2 and S3

D. All of S1, S2 and S3

Answer: A.

An explicit field can encode memory or a register. An implied accumulator comes from the opcode or machine convention, so it needs no field.

4. Instruction-format bit budgets: Questions 9-11

Allocate ceil(log2 N) bits per field, then round the whole instruction only when byte alignment requires it.

Question 9: opcode capacity with addressing-mode and register fields

GATE 2024

A processor with 16 general purpose registers uses a 32-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand fields, and a 16-bit scalar field. If 8 addressing modes are to be supported, the maximum number of unique opcodes possible for every addressing mode is _________

Numerical answer type.

Answer: 32.

Two register fields need 2 x log2 16 = 8 bits; eight modes need 3, and the scalar needs 16. The opcode gets 32 - 8 - 3 - 16 = 5 bits, giving 2^5 = 32 opcodes per mode.

Question 10: expanding opcodes across I-type and R-type formats

GATE 2020

A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a 4-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are 8 distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _______ .

Numerical answer type.

Answer: 14.

Each of 64 registers needs 6 bits. I-type leaves 16 - 6 - 4 = 6 opcode bits, while R-type leaves 16 - 6 - 6 = 4; eight I-type codewords occupy two of the 16 four-bit prefixes, leaving 16 - 2 = 14 R-type opcodes.

Question 11: byte-aligned instruction size and program text

GATE 2016

Consider a processor with 64 registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and a twelve-bit immediate value. Each instruction must be stored in memory in a byte-aligned fashion. If a program has 100 instructions, the amount of memory (in bytes) consumed by the program text is __________ .

Numerical answer type.

Answer: 500 bytes.

Twelve instructions need ceil(log2 12) = 4 opcode bits, and three register identifiers need 3 x 6 = 18. Total size is 4 + 18 + 12 = 34 bits, rounded to 40 bits or 5 bytes, so 100 x 5 = 500 bytes.

5. PC-relative branch displacement: Question 12

Measure a branch offset from the address of the next instruction, not from the branch itself.

Question 12: backward branch offset in bytes

GATE 2017

A RISC machine uses 4-byte instructions. Branch offsets are measured in bytes from the address of the next instruction. Consider this sequence:
i: add R2, R3, R4
i+1: sub R5, R6, R7
i+2: cmp R1, R9, R10
i+3: beq R1, Offset
If the branch target is instruction i, what decimal value is stored in Offset?

Numerical answer type.

Answer: -16 bytes.

Let i start at A; the branch is at A + 12 and next PC at A + 16. The target is A, so offset = A - (A + 16) = -16 bytes; -12 wrongly uses the branch address.

6. Common instruction-format and addressing-mode traps

Write the governing equation before reading the options. Mixed questions become manageable when mode selection, next-PC arithmetic, field allocation, byte rounding, and memory-reference counting remain separate steps.

7. The short version and next practice step

• Translate the instruction into an EA equation or field equation.

• Use the next PC for PC-relative addressing.

• Count instruction fetches separately from operand-memory reads.

• Round only when the storage rule requires it.

Repair a missed answer by naming the failed rule, then redo that question without the options. For timed mixed practice, use the GATE Test Series and write the effective-address or field equation before selecting an answer.