Interrupt-Driven I/O MCQs: 12 Solved Questions with Explanations

An interrupt question usually hides either a control timeline or a unit conversion. Write finish -> save -> vector -> service -> restore for control questions, and keep event rate, time per event, and CPU time in one unit for numericals.

Attempt every item before opening its explanation. For Questions 1 to 9, draw the control path or priority order if the answer is not immediate. For Questions 10 to 12, write the unit beside every intermediate value. Microseconds, milliseconds, bytes, and seconds are the main traps, and a correct formula with inconsistent units still gives a wrong answer.

Interrupt-driven I/O MCQs: attempt rules and core model

A device raises an interrupt. The processor normally finishes the current instruction, saves context, obtains the handler address, runs the ISR, restores context, and resumes. Where a question specifies a different mechanism, use that mechanism instead of importing assumptions from another architecture.

This topic sits inside the wider GATE CS Exam Preparation syllabus, so attempt the questions below without looking ahead.

Interrupt recognition and ISR sequence: Questions 1-3

Question 1: CPU interrupt recognition

GATE 2009

A CPU generally handles an interrupt by executing an interrupt service routine

• A. As soon as an interrupt is raised

• B. By checking the interrupt register at the end of fetch cycle.

• C. By checking the interrupt register after finishing the execution of the current instruction.

• D. By checking the interrupt register at fixed time intervals.

Answer: C.

Finishing the instruction leaves clean saved state. The CPU then enters the ISR.

Question 2: save the PC and branch to the ISR

GATE 2025, Set 1

Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order) are taken by the processor when the interrupt arrives:

(i) The processor saves the content of the program counter.

(ii) The program counter is loaded with the start address of the ISR.

(iii) The processor finishes the present instruction.

Which ONE of the following is the CORRECT sequence of steps?

• A. (iii), (i), (ii)

• B. (i), (iii), (ii)

• C. (i), (ii), (iii)

• D. (iii), (ii), (i)

Answer: A.

Finish the instruction, then save the return PC. Load the ISR address last: (iii) -> (i) -> (ii).

Question 3: full interrupt event order

GATE 2018

The following are some events that occur after a device controller issues an interrupt while process L is under execution.

(P) The processor pushes the process status of L onto the control stack.

(Q) The processor finishes the execution of the current instruction.

(R) The processor executes the interrupt service routine.

(S) The processor pops the process status of L from the control stack.

(T) The processor loads the new PC value based on the interrupt.

Which one of the following is the correct order in which the events above occur?

• A. QPTRS

• B. PTRSQ

• C. TRPQS

• D. QTPRS

Answer: A.

Q finishes, P saves, and T redirects. R runs before S restores: Q -> P -> T -> R -> S.

Vectored interrupts and shared request lines: Questions 4-5

Question 4: what supplies the branch information

ISRO 2023

In a vectored interrupt

• A. The branch address is assigned to a fixed location in memory

• B. The interrupting source supplies the branch information to the processor

• C. The branch address is obtained from a register in the processor

• D. None of these

Answer: B.

A vector identifies the correct handler. Here, the source supplies that branch information.

Question 5: one request line and one grant line

GATE 2005

Which one of the following is true for a CPU having a single interrupt request line and a single interrupt grant line?

• A. Neither vectored interrupt nor multiple interrupting devices are possible.

• B. Vectored interrupts are not possible but multiple interrupting devices are possible.

• C. Vectored interrupts and multiple interrupting devices are both possible.

• D. Vectored interrupt is possible but multiple interrupting devices are not possible.

Answer: C.

Devices can share request and grant lines. The selected device can also supply a vector.

Daisy-chain arbitration and source identification: Questions 6-7

Question 6: priority in a daisy chain

GATE 1996

For the daisy chain scheme of connecting I/O devices, which of the following statements is true?

• A. It gives non-uniform priority to various devices

• B. It gives uniform priority to all devices

• C. It is only useful for connecting slow devices to a processor device

• D. It requires a separate interrupt pin on the processor for each device

Answer: A.

The grant follows physical order. Nearer devices capture it first, creating non-uniform priority.

Question 7: vectored versus daisy-chain handling

GATE 2026, Set 2

Consider the following two statements about interrupt handling mechanisms in a CPU.

S1: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Service Routine (ISR) when compared to that in a vectored interrupt mechanism.

S2: In daisy-chain interrupt mechanism, the CPU polls all the input devices individually to determine the source of the interrupt.

Which one of the following options is correct?

• A. Both S1 and S2 are true

• B. Both S1 and S2 are false

• C. S1 is true and S2 is false

• D. S1 is false and S2 is true

Answer: C.

S1 is true because vectoring identifies the ISR directly. S2 is false because hardware resolves the chain.

Interrupt priority choices: Questions 8-9

Question 8: the most urgent source

GATE 2011

A computer handles several interrupt sources of which of the following are relevant for this question.

Interrupt from CPU temperature sensor (raises interrupt if CPU temperature is too high)

Interrupt from Mouse (raises Interrupt if the mouse is moved or a button is pressed)

Interrupt from Keyboard (raises Interrupt if a key is pressed or released)

Interrupt from Hard Disk (raises Interrupt when a disk read is completed)

Which one of these will be handled at the HIGHEST priority?

• A. Interrupt from Hard Disk

• B. Interrupt from Mouse

• C. Interrupt from Keyboard

• D. Interrupt from CPU temperature sensor

Answer: D.

Overheating threatens the entire system. It therefore outranks routine I/O.

Question 9: device speed and interrupt priority

GATE 1998

Which of the following devices should get higher priority in assigning interrupts?

• A. Hard disk

• B. Printer

• C. Keyboard

• D. Floppy disk

Answer: A.

The hard disk has the highest listed rate. Slower devices tolerate a longer response here.

Interrupt overhead and performance numericals: Questions 10-12

Convert rate to inter-arrival time, use one unit, and count one overhead per interrupt.

Question 10: priority timing range

ISRO 2009

A certain microprocessor requires 4.5 microseconds to respond to an interrupt. Assuming that the three interrupts I1, I2 and I3 require the following execution time after the interrupt is recognized: i. I1 requires 25 microseconds ii. I2 requires 35 microseconds iii. I3 requires 20 microseconds I1 has the highest priority and I3 has the lowest. What is the possible range of time for I3 to be executed assuming that it may or may not occur simultaneously with other interrupts?

• A. 24.5 microseconds to 39.5 microseconds

• B. 24.5 microseconds to 93.5 microseconds

• C. 4.5 microseconds to 24.5 microseconds

• D. 29.5 microseconds to 93.5 microseconds

Answer: B.

Minimum time is 4.5 + 20 = 24.5 microseconds. With I1 and I2 first, (4.5 + 25) + (4.5 + 35) + (4.5 + 20) = 93.5 microseconds, so B gives the range.

Question 11: interrupt mode performance gain

GATE 2005

A device with data transfer rate 10 KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be 4 microsec. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program controlled mode?

• A. 15

• B. 25

• C. 35

• D. 45

Answer: B.

Using the decimal convention implied by the listed answer, 10 KB/sec = 10,000 bytes/sec, so one byte arrives every 100 microseconds. Program-controlled time divided by interrupt overhead is 100/4 = 25.

Question 12: polling time versus interrupt time

GATE 2023

A keyboard connected to a computer is used at a rate of 1 keystroke per second. The computer system polls the keyboard every 10 ms (milli seconds) to check for a keystroke and consumes 100 μs (micro seconds) for each poll. If it is determined after polling that a key has been pressed, the system consumes an additional 200 μs to process the keystroke.

Let T1 denote the fraction of a second spent in polling and processing a keystroke. In an alternative implementation, the system uses interrupts instead of polling. An interrupt is raised for every keystroke. It takes a total of 1 ms for servicing an interrupt and processing a keystroke. Let T2 denote the fraction of a second spent in servicing the interrupt and processing a keystroke.

The ratio T1/T2 is . (Rounded off to one decimal place)

Answer: 10.2.

At 100 polls per second, T1 = (100 x 100 μs) + 200 μs = 10,200 μs = 0.0102 s. Since T2 = 1 ms = 0.001 s, the ratio is 0.0102/0.001 = 10.2.

Interrupt-driven I/O MCQs: reconstruct one complete event

Close the notes and reconstruct one event from device request to return: finish the current instruction -> save PC and status -> identify the vector -> arbitrate among simultaneous sources -> run the ISR -> restore state.

Redo Questions 10 to 12 with a unit ledger: event rate, time per event, accumulated CPU time, and final ratio. A result that changes when microseconds and milliseconds are written beside each number was not reliable.

For the wider comparison of CPU involvement across programmed I/O, interrupts, and DMA, use DMA, Interrupts and Programmed I/O for GATE: Solved Numericals. That explainer compares cross-method calculations. Then return to the ISR path and trace sequencing, vectoring, priority, and per-interrupt overhead.

Use GATE Guidance by Sanchit Sir to rebuild the full computer-architecture sequence. Move to the GATE Test Series after you can reproduce the control path and all three calculations without the answer lines.