Consider the following code sequence having five instructions 𝐼1 to 𝐼5. Each…
2015
Consider the following code sequence having five instructions 𝐼1 to 𝐼5. Each of these instructions has the following format.
OP Ri, Rj, Rk
where operation OP is performed on contents of registers Rj and Rk and the result is stored in register Ri.
𝐼1: ADD R1, R2, R3
𝐼2: MUL R7, R1, R3
𝐼3: SUB R4, R1, R5
𝐼4: ADD R3, R2, R4
𝐼5: MUL R7, R8, R9
Consider the following three statements.
S1: There is an anti-dependence between instructions 𝐼2 and 𝐼5
S2: There is an anti-dependence between instructions 𝐼2 and 𝐼4
S3: Within an instruction pipeline an anti-dependence always creates one or more stalls
Which one of above statements is/are correct?
- A.
Only S1 is true
- B.
Only S2 is true
- C.
Only S1 and S3 are true
- D.
Only S2 and S3 are true
Attempted by 85 students.
Show answer & explanation
Correct answer: B
Answer: Only S2 is true.
I1: writes R1; reads R2, R3.
I2: writes R7; reads R1, R3.
I3: writes R4; reads R1, R5.
I4: writes R3; reads R2, R4.
I5: writes R7; reads R8, R9.
Key point: An anti-dependence (WAR) occurs when an earlier instruction reads a register and a later instruction writes the same register.
Check S1 (I2 vs I5): I2 reads R1 and R3, but I5 writes R7 — no read-then-write on the same register. I2 and I5 actually have a write-after-write on R7, not an anti-dependence. So S1 is false.
Check S2 (I2 vs I4): I2 reads R3 and I4 writes R3, which is a read-then-write on R3. This is an anti-dependence, so S2 is true.
Check S3 (anti-dependence always causes stalls): Not true in general. Anti-dependence is a name dependence that can be eliminated by register renaming or other hardware techniques, so it does not always force pipeline stalls. Therefore S3 is false.
Conclusion: Only the statement that there is an anti-dependence between I2 and I4 is correct.