Remembering that NAND and NOR are universal is easy. Marks are lost when the same idea appears as gate-count minimisation, a substituted-gate network, an absorption-law simplification, or a circuit-output trace. A rushed count also measures the written expression instead of the simpler function underneath. The cure is disciplined signal tracing. NAND and NOR realization problems range from direct recall to multi-level realization. Attempt each one before opening the explanation, and write the intermediate signal after every gate. That small habit makes complements visible and prevents most bubble errors.
Revise the four identities that unlock the set
A gate is universal when repeated use of that gate type can realise every Boolean function. These four constructions are the starting point:
NOT A = A NAND AA AND B = (A NAND B) NAND (A NAND B)NOT A = A NOR AA OR B = (A NOR B) NOR (A NOR B)
The tied-input cases confirm the inverter. For A=0, A NAND A=1 and A NOR A=1. For A=1, both outputs are 0. Thus each tied-input gate produces A'.
For design, NAND naturally supports sum-of-products in NAND-NAND form, while NOR supports product-of-sums in NOR-NOR form. If absorption or De Morgan's law is still slowing you down, first revise the Boolean Algebra and K-map Minimization Guide.
Questions 1-3: identify the universal gate and simplify
Question 1: Identify a universal gate
Which of the following is a universal gate?
A. NOT
B. NAND
C. OR
D. AND
Answer: B. NAND is functionally complete. A NAND A gives NOT, and NANDing A NAND B with itself restores AND. Once NOT and AND exist, OR follows from A OR B = (A'B')'. NOT, OR and AND are not individually universal.
Question 2: Find the false statement about NAND
Which of the following expressions is not True about NAND gates in Boolean Algebra?
A. It is a Universal Gate
B. It is NOT gate of AND gate
C. For variables U and V, NAND is represented as (U · V)'
D. Every Boolean Expression cannot be represented with the help of NAND gate only
Answer: D. Notice the words “not True”. A, B and C correctly describe NAND. D contradicts universality: every Boolean expression can be represented using NAND alone, starting with the NOT and AND constructions above.
Question 3: Simplify an expression before choosing a gate form
Which of the following is equivalent of the Boolean expression given below? A + Ā.B + A.B̅
A. A + B
B. A + B̅
C. B + Ā
D. B̅ + Ā
Answer: A. Use A + ĀB = A + B:
A + ĀB + AB̅ = A + B + AB̅ = A + B.
The last step uses A + AB̅ = A. At (A,B)=(0,1), the original is 0+1+0=1, and A+B=1.
Questions 4-6: use absorption before counting gates
Question 4: Simplify a product-of-sums expression
The Simplified form of Boolean Expression (X+Y+XY) (X+Z) is
A. X+Y+ZX+Y
B. XY-YZ
C. X+YZ
D. XZ+Y
Answer: C. Since X+XY=X, the first factor becomes X+Y. Then (X+Y)(X+Z)=X+YZ. At (X,Y,Z)=(0,1,1), the original is (0+1+0)(0+1)=1, while X+YZ=0+1=1.
Question 5: Count gates only after simplifying AC + ABC
How many gate(s) would be required to implement the following boolean expression after simplification? Expression : AC + ABC
A. 4
B. 1
C. 2
D. 3
Answer: B. Factor first: AC+ABC=AC(1+B)=AC. One 2-input AND gate implements the simplified function. Gates suggested by the unsimplified expression do not count.
Question 6: Let absorption reduce the minimum to zero
The minimum number of NAND gates required to implement the Boolean function A + AB'+ AB'C is equal to
A. 0
B. 1
C. 4
D. 7
Answer: A. Absorb twice: A+AB'=A, then A+AB'C=A. The available input A can connect directly to the output, so zero NAND gates are required. A buffer would count only if buffering were explicitly required.
Questions 7-9: derive exact NAND-only and NOR-only counts
Question 7: Implement WX+Y using only NAND gates
What is the minimum number of 2-input NAND gates required to implement the Boolean function F=WX+Y ?
A. 5
B. 3
C. 2
D. 4
Answer: B. Gate 1 gives N1=(WX)'. Tied-input Gate 2 gives N2=(Y.Y)'=Y'. Gate 3 gives (N1.N2)'=((WX)'.Y')'=WX+Y. For (W,X,Y)=(0,0,1), the signals are N1=1, N2=0, and final output 1, matching F. Two gates cannot create both required complemented inputs and then combine them.
Question 8: Implement AB+C using only NOR gates
What is the minimum number of gates required to implement the Boolean function (AB+C) if we have to use only 2-input NOR gates?
A. 2
B. 3
C. 4
D. 5
Answer: B. Rewrite AB+C=(A+C)(B+C). Gate 1 gives N1=(A+C)', Gate 2 gives N2=(B+C)', and Gate 3 gives (N1+N2)'=(A+C)(B+C)=AB+C. At (A,B,C)=(1,0,0), the signals are N1=0, N2=1, and output 0, matching AB+C.
Question 9: Build 2-input XOR from four NAND gates
What is the minimum number of NAND gates required to implement a 2-input EXCLUSIVE-OR function without using any other logic gate?
A. 3
B. 4
C. 5
D. 6
Answer: B. Use N1=A NAND B, N2=A NAND N1, N3=B NAND N1, and F=N2 NAND N3. The four rows are 00 -> 0, 01 -> 1, 10 -> 1, 11 -> 0, exactly XOR. Sharing N1 avoids constructing both complements separately.
Questions 10-12: trace substituted and multi-level networks
Question 10: Replace every 2-input AND with NAND
The following expression was to be realized using 2-input AND and OR gates. However, during the fabrication all 2-input AND gates were mistakenly substituted by 2-input NAND gates. (a.b).c + (a'.c).d + (b.c).d + a. d What is the function finally realized ?
A. 1
B. a' + b' + c' + d'
C. a' + b + c' + d'
D. a' + b' + c + d'
Answer: C. Preserve the two-gate grouping. The four substituted chains give ab+c', a'c+d', bc+d', and a'+d'. ORing them gives ab+c'+a'c+d'+bc+a'+d'. Absorb a'c into a', use c'+bc=c'+b, then b+ab=b. The result is a'+b+c'+d'.
Question 11: Simplify a seven-NOR circuit
What is the Boolean expression for the output \(f\) of the combinational logic circuit of NOR gates given below?
A. \(\overline{Q+R}\)
B. \(\overline{P+Q}\)
C. \(\overline{P+R}\)
D. \(\overline{P+Q+R}\)
Answer: A. Let A=(P+Q)', B=(Q+R)', C=(P+R)', and D=(Q+R)'. Then E=(A+B)'=(P+Q)(Q+R) and F=(C+D)'=(P+R)(Q+R). Therefore:
E+F=(Q+R)[(P+Q)+(P+R)]=(Q+R)(P+Q+R)=Q+R.
The final NOR gives f=(Q+R)'.
Question 12: Recognise XOR inside a NOR network
Which of the following logic operations is performed by the following given combinational circuit ?
A. EXCLUSIVE-OR
B. EXCLUSIVE-NOR
C. NAND
D. NOR
Answer: A. Let A=NOR(x,y)=(x+y)'. The upper middle NOR gives B=NOR(x,A)=x'A'=x'(x+y)=x'y. The lower one gives C=NOR(y,A)=y'A'=y'(x+y)=xy'. The final gate is OR, so f=B+C=x'y+xy'=x XOR y. Its outputs are 00 -> 0, 01 -> 1, 10 -> 1, 11 -> 0.
Turn the wrong options into four reusable trap checks
Trap | Check before answering |
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Count before simplifying | Apply absorption first, as in Questions 5 and 6. |
Use the wrong normal form | Choose NAND-NAND for SOP and NOR-NOR for POS, as in Questions 7 and 8. |
Lose a complement at a bubble | Name every intermediate signal, as in Questions 10-12. |
Count logic levels instead of gates | Draw and number each physical gate, as in Question 9. |
Keep this rewrite sheet beside the trap checks:
target | first rewrite |
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For foundational universal-gate formulas, tied-input construction, and completeness tests, work through NAND and NOR Universal Gates: 12 Solved MCQs. Then apply those foundations to the gate minimisation, substituted-network, and multi-level trace problems above.
Score the set and choose the next practice step
10-12 correct: redraw Questions 10-12 without looking.
7-9 correct: redo the NAND and NOR identities, then Questions 7-9.
0-6 correct: return to the identities and Questions 1-6 before another mixed set.
Use the result to judge your current understanding, not to predict an official exam result. Follow these 12 with a second mixed round of Universal Realization practice, choosing different expressions and gate networks.
The short version
Simplify first, choose a gate-friendly form, label each intermediate complement, and verify one discriminating input row. If the concepts still feel weak, start with GATE Guidance by Sanchit Sir. If you are ready to drill, move to the GATE Test Series. To compare broader preparation routes, use GATE CS Exam Preparation. The method stays the same in every network: simplify, rewrite, label, trace, and only then count. Repeat that sequence until the gate count follows naturally from the simplified function.
