Flip-Flops and Conversion MCQs: 12 Solved Questions with Explanations

A student may remember four truth tables and still lose the mark by mixing up active-high SR behaviour with NAND-latch behaviour, or by changing Q before applying the clock rule. Start with the present state and the device rule: active-high SR behaviour differs from NAND-latch behaviour, and a clocked device changes only at its active trigger. Attempt each question before reading its answer. Use Qn for the present state and Qn+1 for the next state. Students who need the full subject sequence can use GATE Guidance by Sanchit Sir.

The conversion method to use before the MCQs

Keep this reference set beside you:

• D flip-flop: D = Qn+1

• T flip-flop: T = Qn XOR Qn+1

• JK flip-flop: Qn+1 = JQn' + K'Qn

• Active-high SR flip-flop: Qn+1 = S + R'Qn, with S = R = 1 excluded

Conversion means wiring the available flip-flop so that it reproduces the target next state for both possible present states.

For a JK-to-D conversion, choose J = D and K = D'. If Qn = 0, the JK equation reduces to Qn+1 = J = D. If Qn = 1, it reduces to Qn+1 = K' = (D')' = D.

Thus (D,Qn) = (0,0) -> 0, (0,1) -> 0, (1,0) -> 1 and (1,1) -> 1. Every row matches D. Use Flip-Flop Conversion for GATE: 4-Step Excitation Recipe when you want the complete excitation-table derivation.

Questions 1-2: invalid SR states and oscillation

Question 1 | GATE previous-year question from 2004

In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in

• A. Q = 0, Q' = 1

• B. Q = 1, Q' = 0

• C. Q = 1, Q' = 1

• D. Indeterminate states

Answer: C. A NAND output is 1 whenever either input is 0. Therefore S = 0 forces one output high and R = 0 forces the other high, giving Q = 1 and Q' = 1. This is forbidden because the outputs are no longer complements. For an active-high NOR SR latch, the forbidden input is instead S = R = 1.

Question 2 | GATE previous-year question from 2007

Which of the following input sequences for a cross-coupled R-S flip-flop realized with two NAND gates may lead to an oscillation ?

• A. 11, 00

• B. 01, 10

• C. 10, 01

• D. 00, 11

Answer: D. The input 00 first drives both outputs to 1. If both inputs then change to 11 together, the symmetric feedback loop must resolve according to tiny propagation-delay differences. It can oscillate or become metastable before settling. Inputs 01 and 10 each select a definite set or reset state.

Questions 3-4: hold and toggle conditions

Question 3 | NTA UGC NET Paper 2 previous-year question from 2018

In RS flip-flop, the output of the flip-flop at time (t+1) is same as the output at time t, after the occurrence of a clock pulse if

• A. S = R = 1

• B. S = 0, R = 1

• C. S = 1, R = 0

• D. S = R = 0

Answer: D. For an active-high SR flip-flop, S = 0, R = 0 gives Q(t+1) = 0 + 1.Q(t) = Q(t). Present states 0 and 1 are both retained. The other rows are 01 -> reset, 10 -> set and 11 -> invalid.

Question 4 | NTA UGC NET Paper 2 previous-year question from 2016

In a positive-edge-triggered JK flip-flop, if J and K both are high then the output will be _____ on the rising edge of the clock.

• A. No change

• B. Set

• C. Reset

• D. Toggle

Answer: D. With J = K = 1, a present state Qn = 0 produces Qn+1 = 1, while Qn = 1 produces Qn+1 = 0. The positive-edge-triggered device toggles once on the rising edge. This is not repeated level-sensitive toggling.

Questions 5-6: characteristic equations

Question 5 | ISRO previous-year question from 2007

The characteristic equation of an SR flip-flop is given by

• A. Qn+1 = S + RQn

• B. Qn+1= RQ'n + SQn

• C. Qn+1= S' + RQn

• D. Qn+1 = S + R'Qn

Answer: D. Check Qn+1 = S + R'Qn over the valid rows. S=0,R=0 gives Qn+1=Qn; S=1,R=0 gives 1; and S=0,R=1 gives 0. The equation does not make the excluded input S=R=1 valid.

Question 6 | RSSB Senior Computer Instructor previous-year question from 2025

What is the characteristic equation of a T flip-flop?

• A. Q* = T + Q

• B. Q* = T

• C. Q* = T . Q

• D. Q* = T ⊕ Q

Answer: D. Here Q* is the next state. For hold, T=0,Q=0 -> Q*=0 and T=0,Q=1 -> Q*=1. For toggle, T=1,Q=0 -> Q*=1 and T=1,Q=1 -> Q*=0. The same XOR relationship gives the excitation shortcut T = Qn XOR Qn+1.

Questions 7-8: D input and clock-edge triggering

Question 7 | Coal India MT previous-year question from 2020

In a D flip flop the out-put state Q is related with D input in what way?

• A. Q is dependent of D

• B. Q is same as D

• C. Q is independent of D

• D. Q is complement of D

Answer: B. The characteristic equation is Qn+1 = D. A sampled D=0 makes the next Q 0, while a sampled D=1 makes it 1. After the active clock edge, Q holds that sampled value until the next valid trigger.

Question 8 | Coal India MT previous-year question from 2020

A negative edge triggered flip flop transfers data from input to output on the:

• A. LOW to HIGH transition of clock pulse

• B. BEFORE transition of clock pulse

• C. HIGH to LOW transition of clock pulse

• D. WITHOUT transition of clock pulse

Answer: C. A negative edge is the transition CLK: 1 -> 0. A positive edge is CLK: 0 -> 1. A clock held steadily high or low has no transition, so it is not an edge.

Questions 9-10: race-around and timing reliability

Question 9 | NTA UGC NET Paper 2 previous-year question from 2014

Which of the following flip-flops is free from race condition ?

• A. T flip-flop

• B. SR flip-flop

• C. Master-slave JK flip-flop

• D. None of the above

Answer: C. During the first clock phase, the master samples J,K while the slave is closed. During the opposite phase, the slave copies the master's fixed state. Therefore J=K=1 causes one toggle per clock cycle, not repeated toggles during one active clock level.

Question 10 | RSSB Senior Computer Instructor previous-year question from 2025

If the data input (D) of a positive edge-triggered D flip-flop changes from 0 to 1 right during the rising edge of the clock signal, what will the resulting output Q be?

• A. Q will become 0

• B. Q will become 1

• C. Q may be unpredictable due to timing violation

• D. Q will not change

Answer: C. D changed inside the sampling window instead of remaining stable for the required setup time before, and hold time after, the 0 -> 1 clock edge. The flip-flop may enter metastability and eventually resolve to 0 or 1. Neither result is guaranteed.

Questions 11-12: compare the devices, then identify the storage element

Question 11 | ISRO previous-year question from 2016

The functional difference between SR flip-flop and JK flip-flop is that

• A. JK Flip-flop is faster than SR flip-flop

• B. JK flip-flop has a feedback path

• C. JK flip-flop accepts both inputs 1

• D. none of them

Answer: C. For an active-high SR flip-flop, S=R=1 is invalid. For a JK flip-flop, J=K=1 is defined and gives Qn+1 = Qn'. Speed cannot be inferred without implementation delays, and both storage devices rely on feedback.

Question 12 | NTA UGC NET Paper 2 previous-year question from 2023

Which of the following circuit is used to store one bit of data ?

• A. Encoder

• B. Decoder

• C. Flip-Flop

• D. Register

Answer: C. One flip-flop has two stable logical states, 0 and 1, so it stores one bit. Encoders and decoders are combinational circuits. A register is a group of flip-flops and stores a multi-bit word, such as eight bits with eight flip-flops.

Fast conversion checklist and the next practice step

Sort each miss into one of five causes: invalid or hold rows, edge or toggle behaviour, characteristic equations, conversion, or timing reliability. Redo only the category you missed after one day, then attempt the complete set again after one week.

Before finalising any flip-flop answer:

1. Identify whether the inputs are active-high or active-low.

2. Write Qn before changing anything.

3. Derive Qn+1 from the applicable input and clock rule.

4. Verify both Qn=0 and Qn=1.

A conversion is complete only when every valid input and state row agrees. Use Sequential Circuits MCQs: 11 Solved GATE Questions for a wider counter-focused set. For structured subject preparation across the syllabus, use GATE CS Exam Preparation Courses & Test Series.