NAND and NOR Universal Gates MCQs: 12 Solved Questions with Explanations

Many learners can recall a NAND or NOR truth table, then lose the mark when the question changes form, ties both inputs together, applies De Morgan's law, or tests whether another gate set is functionally complete. The 12 questions below move from gate identification to NAND-only construction to functional completeness, and each one names the exam and year it came from. Select an option and write one Boolean step before you check the answer, because the written step is what survives an unfamiliar gate symbol. Universal gates sit inside Digital Electronics, which the GATE CS Exam Preparation category maps end to end, and KnowledgeGate carries over 30 questions on NAND and NOR alone.

NAND and NOR formulas: truth tables, De Morgan and tied inputs

NAND means AND followed by inversion: Y = (A.B)'. NOR means OR followed by inversion: Y = (A+B)'. De Morgan's identities connect them: (A.B)' = A' + B' and (A+B)' = A'.B'.

The NAND outputs are 1, 1, 1, 0, while the NOR outputs are 1, 0, 0, 0 for 00, 01, 10, 11. A quick memory check is that NAND becomes 0 only when every input is 1; NOR becomes 1 only when every input is 0.

For A=1, B=0, A.B=0, so NAND is 1; A+B=1, so NOR is 0. Tying the inputs creates NOT. For A=1, A NAND A=(1.1)'=0 and A NOR A=(1+1)'=0.

Building OR from NAND alone: let N1=A NAND A=A' and N2=B NAND B=B'. Then Y=N1 NAND N2=(A'.B')'=A+B.

Universal-gate MCQs 1-3: identification and functional completeness

Question 1

HPSC 2021.

Which among the following logic gates are known as universal gates?

• A. XOR, NAND, OR

• B. OR, NOT, XOR

• C. NOR, NAND, XNOR

• D. NOR, NAND

Answer: D. NOR, NAND. A universal gate type can reproduce NOT, AND and OR, and hence any Boolean function. NAND and NOR each do this alone. XNOR cannot, which rules out option C. Option A mixes NAND with XOR and OR, and option B holds no universal gate at all, so only option D lists exactly the two universal types.

Question 2

Beltron Programmer 2025, Shift-1.

Which property makes the NAND gate a "universal gate"?

• A. It requires fewer transistors than other gates.

• B. It operates at higher speeds.

• C. It consumes less power.

• D. It can implement AND, OR, and NOT gates when combined.

Answer: D. It can implement AND, OR, and NOT gates when combined. Tied NAND inputs give NOT. If N=A NAND B, then N NAND N=A.B, which gives AND. NANDing separately inverted inputs gives OR. Universality describes this functional completeness, not speed, power or transistor count.

Question 3

UGC NET 2008, Paper 2 (December).

An example of a universal building block is

• A. EX-OR gate

• B. AND gate

• C. OR gate

• D. NOR gate

Answer: D. NOR gate. A NOR A=A' gives NOT. (A NOR A) NOR (B NOR B)=A.B gives AND. (A NOR B) NOR (A NOR B)=A+B gives OR. Each expression uses NOR alone, so rebuilding all three proves that NOR is universal.

NAND and NOR MCQs 4-6: symbols, expressions and De Morgan's law

Question 4

UP Police 2017, Paper 2 - Subject Oriented (Shift I).

What does the small bubble on the NAND gate's logic symbol mean with respect to the output?

• A. The output is inverted

• B. The output is enabled

• C. The output is disabled

• D. None of these

Answer: A. The output is inverted. The AND-shaped body represents A.B; the output bubble complements the whole result to (A.B)'. With A=B=1, AND gives 1 and the bubble changes it to 0. It is an inversion marker, not an enable or disable input.

Question 5

UP Police 2017, Paper 2 - Subject Oriented (Shift I).

If 'a' and 'b' are the inputs and 'O' is the output, then which of the following represents output of NAND gate?

• A. O=a

• B. O=(a.b)'

• C. O=ab

• D. O=(a+b)'

Answer: B. O=(a.b)'. AND first produces a.b, then output inversion produces (a.b)'. Option C is AND and option D is NOR. At a=1, b=1, NAND gives 0, as option B requires.

Question 6

UP Police 2016, Paper 2 - Subject Oriented (Shift I).

According to De Morgan's theorem, a NOR gate is equivalent to:

• A. An AND gate with inverted output

• B. An OR gate with inverted inputs

• C. An AND gate with inverted inputs

• D. An OR gate without inversion

Answer: C. An AND gate with inverted inputs. Apply De Morgan to NOR: (A+B)'=A'.B'. That is AND receiving two inverted inputs. The bubbles move from one output to both inputs when the operation changes. Option A is (A.B)', which is NAND.

Universal-gate MCQs 7-9: tied inputs and gate construction

Question 7

Indian Space Research Organization 2023.

The resulting logic circuit obtained when both inputs of NOR and NAND gates are connected together is:

• A. AND

• B. XOR

• C. OR

• D. NOT

Answer: D. NOT. With common input A, NAND gives (A.A)'=A' and NOR gives (A+A)'=A'. At A=0, both produce 1; at A=1, both produce 0, exactly matching NOT. The identities A.A=A and A+A=A explain why tying works for both gate families.

Question 8

Indian Space Research Organization 2017, May.

What is the minimum number of two-input NAND gates used to perform the function of a two-input OR gate?

• A. One

• B. Two

• C. Three

• D. Four

Answer: C. Three. Gate 1 gives A'; Gate 2 gives B'; Gate 3 gives (A'.B')'=A+B. For A=0, B=1, the intermediate outputs are 1 and 0, whose NAND is 1, matching OR. Two gates cannot create both complements and combine them.

Question 9

GATE 1999, Computer Science.

Which of the following expressions is not equivalent to NOT X, denoted X′?

• A. X NAND X

• B. X NOR X

• C. X NAND 1

• D. X NOR 1

Answer: D. X NOR 1. X NAND X=X', X NOR X=X', and X NAND 1=(X.1)'=X'. But X NOR 1=(X+1)'=1'=0 for either value of X, so it is constant zero. Test X=0: an inverter should give 1, but option D still gives 0.

Universal-gate MCQs 10-12: truth tables and deeper completeness tests

Question 10

DSSSB 2021, TGT - Shift 4.

Which gate is represented by the following truth table?

A B C | Q

0 0 0 | 1

0 0 1 | 1

0 1 0 | 1

0 1 1 | 1

1 0 0 | 1

1 0 1 | 1

1 1 0 | 1

1 1 1 | 0

• A. NOR

• B. NAND

• C. XOR

• D. XNOR

Answer: B. NAND. Three-input AND is 1 only at 111. Complementing it makes the output 0 only at 111 and 1 on the other seven rows. Thus Q=(A.B.C)', a three-input NAND. The unique 0 row is the fastest recognition clue. NOR also gives 1 at 000, but gives 0 at 001, so the second row rejects NOR.

Question 11

GATE 1999, Computer Science.

Which of the following set(s) of components is/are sufficient to implement any arbitrary Boolean function?

a) XOR gates and NOT gates

b) 2-to-1 multiplexers

c) AND gates and XOR gates

d) Three-input gates that output (A.B) + C for inputs A, B and C

• A. a and d

• B. b and c

• C. c only

• D. All of the above

Answer: B. b and c. A 2-to-1 MUX is complete through F=S'.I0+S.I1, using constants on data inputs. Choosing a variable as S recursively builds any truth table. AND plus XOR is complete because X'=X XOR 1 and A+B=(A XOR B) XOR (A.B). XOR plus NOT cannot generate AND, while (A.B)+C is monotone and cannot generate inversion.

Question 12

UGC NET 2018, Paper 2 (December).

Which of the following statements are true?

(i) Every logic network is equivalent to one using just NAND gates or just NOR gates.

(ii) Boolean expressions and logic networks correspond to labelled acyclic digraphs.

(iii) No two Boolean algebras with n atoms are isomorphic.

(iv) Non-zero elements of finite Boolean algebras are not uniquely expressible as joins of atoms.

Choose the correct answer from the code given below:

• A. (i) and (iv) Only

• B. (i), (ii) and (iii) Only

• C. (i) and (ii) Only

• D. (ii), (iii) and (iv) Only

Answer: C. (i) and (ii) Only. Statement (i) follows from NAND and NOR completeness. Statement (ii) describes labelled, directed dependency graphs without combinational cycles. Statement (iii) is false because finite Boolean algebras with the same atom count are isomorphic through an atom-to-atom mapping. Statement (iv) is false because each element has a unique expression as a join of atoms.

Fast checks that prevent NAND and NOR mistakes

1. Translate the symbol into an expression first. An output bubble complements the whole output; an input bubble complements one variable.

2. Test 00 and 11. NAND and NOR separate immediately on these rows. A claimed inverter must map 0 to 1 and 1 to 0.

3. Name every intermediate wire in minimum-count problems. The three-NAND OR circuit requires A', B', then A+B.

4. Do not call a set universal merely because it contains two gate types. Prove NOT plus an AND or OR basis, or use a known complete construction such as a 2-to-1 MUX with constants at its inputs.

The short version and next practice step

Memorise (A.B)' and (A+B)', use tied inputs for NOT, and apply De Morgan before counting gates. Redo Questions 6, 8, 9 and 11 without notes; they test the shifts from symbol to algebra, circuit and completeness. If the algebra still feels slow, solve Boolean Algebra and K-Map MCQs. For the next hardware layer, try Combinational Circuits MCQs. Use GATE Guidance by Sanchit Sir for the full Digital Electronics sequence and topic-wise practice.