Consider an instruction pipeline with five stages without any branch…

Concept. In a synchronous pipeline the clock period is fixed by the slowest stage, so cycle time = max(stage delay) + buffer delay. Every instruction advances one stage per cycle, and a control hazard (a taken branch) wastes cycles: instructions fetched after the branch but before its outcome is known are flushed. The number of wasted cycles equals the number of stages between Fetch and the stage where the branch is resolved.

Application.

1. Clock period: the largest stage delay is FO = 10 ns; adding the 1 ns buffer gives cycle time = 10 + 1 = 11 ns.

2. Branch resolution: the branch I4 is resolved in its Execute stage (EI), the 4th stage. I4 is fetched in cycle 4, so its EI finishes at cycle 4 + 3 = 7. The outcome is known only at the end of cycle 7.

3. Flushed fetches: while I4 moves DI→FO→EI (cycles 5, 6, 7), the next sequential instructions I5, I6, I7 are fetched on the wrong path and must be discarded — 3 wasted cycles.

4. Fetch schedule: I1–I4 are fetched in cycles 1–4; I5–I7 (wrong path, flushed) in cycles 5–7; the target stream I9, I10, I11, I12 is fetched in cycles 8, 9, 10, 11. The last useful fetch is in cycle 11.

5. Drain: an instruction needs all 5 stages, so the instruction fetched in cycle 11 writes its result (WO) 4 cycles later, in cycle 11 + 4 = 15. The program finishes at the end of cycle 15.

Result. Total cycles = 15, so time = 15 × 11 ns = 165 ns.

Cross-check. Count the cycle slots: 4 (I1–I4) + 3 (flushed I5–I7) + 4 (I9–I12) = 11 fetch cycles, plus 4 more cycles to drain the final instruction through the remaining stages = 15 cycles. 15 × 11 = 165 ns, consistent with the schedule above.