A non-pipelined instruction execution unit operating at 2 GHz takes an average…
2024
A non-pipelined instruction execution unit operating at 2 GHz takes an average of 6 cycles to execute an instruction of a program P. The unit is then redesigned to operate on a 5-stage pipeline at 2 GHz. Assume that the ideal throughput of the pipelined unit is 1 instruction per cycle. In the execution of program P, 20% instructions incur an average of 2 cycles stall due to data hazards and 20% instructions incur an average of 3 cycles stall due to control hazards. The speedup (rounded off to one decimal place) obtained by the pipelined design over the non-pipelined design is _________
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Correct answer: 3
Key idea: compute the average cycles per instruction (CPI) for the pipelined design including stalls, then compare it to the non-pipelined CPI.
Average stall due to data hazards = 20% × 2 cycles = 0.2 × 2 = 0.4 cycles per instruction.
Average stall due to control hazards = 20% × 3 cycles = 0.2 × 3 = 0.6 cycles per instruction.
Total average stalls = 0.4 + 0.6 = 1.0 cycles per instruction.
CPI of the pipelined design = ideal 1 + average stalls 1.0 = 2.0 cycles per instruction.
CPI of the non-pipelined design = 6 cycles per instruction (given).
Speedup = (time per instruction non-pipelined) / (time per instruction pipelined) = CPI_non / CPI_pipe = 6 / 2 = 3.0.
Final answer: 3.0 (rounded to one decimal place)
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