Processor X1, operating at 2 GHz, has a standard five-stage RISC instruction…

Processor X1, operating at 2 GHz, has a standard five-stage RISC instruction pipeline with a base CPI (cycles per instruction) of 1 when there are no pipeline hazards. In program P, 30% of the instructions are branch instructions, and each branch causes a two-cycle stall due to control hazards. Processor X2 operates at the same clock frequency and adds a branch prediction unit (BPU). A correctly predicted branch causes no stall; a wrongly predicted branch incurs the same two-cycle stall as in X1. Neither processor has structural or data hazards. If the BPU prediction accuracy is 80%, find the speedup of X2 over X1 for program P, rounded to two decimal places.