A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction…
2022
A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor X2 operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for X1 and X2. If the BPU has a prediction accuracy of 80%, the speed up (rounded off to two decimal places) obtained by X2 over X1 in executing P is____________.
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Correct answer: 1.43
Key idea: at the same clock rate, execution time is proportional to CPI, so compute CPI for each processor and take their ratio.
Base CPI without hazards = 1.
For processor X1: 30% of instructions are branches and each branch causes a 2-cycle stall, so extra CPI = 0.3 × 2 = 0.6. Thus CPI_X1 = 1 + 0.6 = 1.6.
For processor X2 with 80% prediction accuracy: only mispredicted branches (20% of branches) cause the 2-cycle stall. Extra CPI = 0.3 × 0.2 × 2 = 0.12. Thus CPI_X2 = 1 + 0.12 = 1.12.
Speedup = CPI_X1 / CPI_X2 = 1.6 / 1.12 ≈ 1.428571…
Rounded to two decimal places, the speedup ≈ 1.43.
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