Processor X1, operating at 2 GHz, has a standard five-stage RISC instruction pipeline with a base CPI…

Question

Processor X1, operating at 2 GHz, has a standard five-stage RISC instruction pipeline with a base CPI (cycles per instruction) of 1 when there are no pipeline hazards. In program P, 30% of the instructions are branch instructions, and each branch causes a two-cycle stall due to control hazards. Processor X2 operates at the same clock frequency and adds a branch prediction unit (BPU). A correctly predicted branch causes no stall; a wrongly predicted branch incurs the same two-cycle stall as in X1. Neither processor has structural or data hazards. If the BPU prediction accuracy is 80%, find the speedup of X2 over X1 for program P, rounded to two decimal places.

Accepted Answer

Correct answer: 1.42 to 1.43 — Concept: At the same clock frequency and for the same instruction count, execution time is proportional to average CPI. A branch penalty contributes branch frequency × average penalty per branch to CPI. Therefore, the speedup of X2 over X1 is CPI(X1) / CPI(X2). Application: Compute the average CPI of each processor and then take their ratio. For X1, every branch incurs two stall cycles. Extra CPI = 0.30 × 2 = 0.60, so CPI(X1) = 1 + 0.60 = 1.60. For X2, the misprediction rate is 1 − 0.80 = 0.20. Only these branches incur the two-cycle stall. Extra CPI = 0.30 × 0.20 × 2 = 0.12, so CPI(X2) = 1 + 0.12 = 1.12. Speedup = 1.60 / 1.12 = 10/7 = 1.428571…, which rounds to 1.43 to two decimal places. Cross-check: For 100 instructions, X1 takes 100 + 30 × 2 = 160 cycles. X2 mispredicts 20% of 30 branches, i.e. 6 branches, and takes 100 + 6 × 2 = 112 cycles. The ratio 160/112 is again 10/7 ≈ 1.43. The official GATE numerical-answer key accepts 1.42–1.43, so the stored NAT range should match that accepted range.

Processor X1, operating at 2 GHz, has a standard five-stage RISC instruction…