8085 & 8086 Basics MCQs: 12 Solved Questions with Explanations

Knowing that the 8085 is an 8-bit processor and the 8086 is a 16-bit processor is not enough for a close MCQ. Change ALU width to address-bus width, or segment value to physical address, and a familiar fact can suddenly look uncertain.

ALU width, address space, segment arithmetic, instructions, flags, interrupts and stack behaviour demand different first checks. Attempt each MCQ before reading the answer, then recompute the worked values and compare the option labels. The CS Fundamentals for Exams & Placements page gives the wider study route. Instruction Structure MCQs: 12 Solved Questions on Opcodes, Address Formats and Bit Allocation owns general opcode fields, address formats and encoding numericals; this set stays with 8085/8086-specific buses, instructions, flags, interrupts and stack behaviour.

Related reading: CPU organisation MCQs and interrupts and programmed I/O.

1. Separate ALU width, data width and address width

Name the width being asked. The 8085 has an 8-bit ALU and data path, but 16 address lines:

16 address bits -> 2^16 addresses -> 65,536 bytes -> 64 KB

Eight data bits move per basic transfer; the 16-bit address selects one of 65,536 byte locations.

Question 1: 8085 ALU width (UGC NET, August 2016)

8085 microprocessor has ____ bit ALU.

• A. 32

• B. 16

• C. 8

• D. 4

Answer: C. 8. The ALU operates on 8-bit operands. The separate 16-bit address bus does not make the ALU 16-bit.

Question 2: 8085 address bus (UGC NET, November 2017)

In 8085 microprocessor the address bus is of __________ bits.

• A. 4

• B. 8

• C. 16

• D. 32

Answer: C. 16. Lines A0 through A15 form 2^16 = 65,536 addresses, and 65,536 / 1024 = 64 KB. They select locations, not data width.

2. Compute 8086 memory capacity and physical addresses

The 8086 identifies 2^20 = 1,048,576 byte locations, or 1 MB here. In real mode, physical address = segment × 16 + offset. Multiplying by 16 shifts the segment left one hexadecimal digit.

Question 3: 8086 address space (ISRO, 2008)

The address space of 8086 CPU is

• A. one Megabyte

• B. 256 Kilobytes

• C. 1 K Megabytes

• D. 64 Kilobytes

Answer: A. one Megabyte. Twenty address bits give 2^20 = 1,048,576 byte locations. The 64 KB distractor belongs to the 8085 calculation.

Question 4: 8086 physical address (CDAC CCAT, 2025)

In the 8086, the physical address is computed as:

• A. Segment + Offset

• B. Segment × 16 + Offset

• C. Segment × 10 + Offset

• D. Segment × 8 + Offset

Answer: B. Segment × 16 + Offset. For segment = 1234H and offset = 5678H, shift once and add:

12340H + 5678H = 179B8H

Decimal 16 equals 10H; option C says decimal 10.

For generic register roles, common-bus selection, memory-line sizing and clock period, use CPU Organization Basics MCQs: 12 Solved Questions with Explanations. This set focuses instead on 8085/8086-specific bus multiplexing, opcodes, flags, interrupts and stack behaviour.

3. Follow the multiplexed bus and register data movement

The 8085 shares AD0-AD7 between the low address byte and data. For 2050H, A15-A8 carry 20H; AD7-AD0 first carry 50H. ALE latches 50H, freeing those lines for data.

Question 5: ALE in the 8085 (CDAC CCAT, 2025)

ALE in the 8085 stands for:

• A. Address Latch Enable

• B. Arithmetic Logic Extension

• C. Address Line Encoder

• D. Asynchronous Latch Enable

Answer: A. Address Latch Enable. ALE makes the latch preserve lower address byte 50H before the shared lines carry data.

Question 6: MOV A, B (DSSSB, 2022)

Which of the following statements is correct about "MOV A, B" instruction of the 8085?

• A. It is a 2 byte instruction.

• B. Its operation code is 11.

• C. Its right most 7 bit represents the operand B.

• D. Its addressing mode is "Register address mode".

Answer: D. Its addressing mode is "Register address mode". Both operands are registers. In 01 DDD SSS, A = 111 and B = 000, giving 01 111 000 = 01111000₂ = 78H, one byte.

4. Decode immediate and register arithmetic instructions

ADI data8 adds immediate data to A; MVI A, data8 has an opcode and data byte; ADD B adds register B to A.

Question 7: ADI (DSSSB, 2022)

Which of the following is the operation of the ADI instruction of the 8085?

• A. Add immediate 8 bits data to Program Counter (PC).

• B. Add register data to accumulator.

• C. Add immediate 8 bits data to accumulator.

• D. Add register data to Program Counter (PC).

Answer: C. Add immediate 8 bits data to accumulator. ADI performs A <- A + data8. PC advances past the instruction but is not the arithmetic destination; ADD B uses a register source.

Question 8: MVI A, 32H (DSSSB, 2022)

Which of the following statements is/are true about "MVI A, 32H" instruction of the 8085? (i) It is a 2-byte instruction. (ii) It moves the hexadecimal data 32H in the accumulator.

• A. Only (i)

• B. Only (ii)

• C. Both (i) and (ii)

• D. Neither (i) nor (ii)

Answer: C. Both (i) and (ii). Its bytes are opcode | 32H: one identifies MVI A, and the other leaves A = 32H.

Question 9: ADD B (DSSSB, 2022)

Which of the following statements is INCORRECT about "ADD B" instruction of the 8085?

• A. It is used to add the content of register B to Accumulator.

• B. Its code in hexa-decimal is 80H.

• C. Its operand is B whose code is 101.

• D. It uses the "register" addressing mode.

Answer: C. Its operand is B whose code is 101. ADD B is register-addressed opcode 80H. Its register field is B = 000; 101 identifies L.

5. Calculate AC and CY from the actual hexadecimal addition

Auxiliary Carry records a carry from bit 3 to bit 4, so inspect the low nibbles. Carry records a carry out of bit 7, so inspect the complete 8-bit addition. A final result of zero does not by itself tell you either flag.

Question 10: Auxiliary Carry and Carry Flag (CDAC CCAT, 2017)

What are the states of the Auxiliary Carry (AC) and Carry Flag (CY) after executing the following 8085 program?

MVI A, FFH

MVI B, 01H

MOV H, A

ADD B

• A. AC = 0 and CY = 0

• B. AC= 0 and CY=1

• C. AC=1 and CY=0

• D. AC=1 and CY=1

Answer: D. AC=1 and CY=1. MOV H, A copies FFH without changing the later operands. Then FFH + 01H = 100H: stored result 00H, ninth-bit carry CY = 1. Also, FH + 1H = 10H, so the nibble carry sets AC = 1.

6. Count the 8085 hardware interrupt inputs

The five hardware interrupt inputs, from highest to lowest standard priority, are TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR. Software RST instructions are a different classification and must not be added to this pin count.

Question 11: Hardware interrupts (UGC NET, June 2016)

8085 microprocessor has _____ hardware interrupts.

• A. 2

• B. 3

• C. 4

• D. 5

Answer: D. 5. TRAP is the non-maskable highest-priority input; INTR is the general non-vectored input.

7. Track the top of the 8085 stack with SP

PC points to the next instruction; the 16-bit SP addresses the stack top. A two-byte push changes SP = 4000H to 3FFEH, showing that the stack grows towards lower addresses.

Question 12: Stack Pointer function (TPSC Assistant Programmer, 2025)

What is the function of the Stack Pointer (SP) in the 8085 microprocessor ?

• A. Points to the next instruction to be executed

• B. Points to the top of the stack in memory

• C. Holds the address of the data to be fetched

• D. Holds the data to be processed

Answer: B. Points to the top of the stack in memory. The 4000H -> 3FFEH push shows its movement. Option A defines PC; C and D do not define SP.

8. Answer key, trap map and the next revision step

Q1 C, Q2 C, Q3 A, Q4 B, Q5 A, Q6 D, Q7 C, Q8 C, Q9 C, Q10 D, Q11 D, Q12 B

For a second attempt, recompute 2^16 = 65,536 bytes, 12340H + 5678H = 179B8H, MOV A, B = 78H, FH + 1H = 10H and FFH + 01H = 100H before looking at the key. That sequence targets the traps instead of merely rereading answers.

The short version

The 8085 has an 8-bit ALU and a 16-bit address bus. The 8086 exposes a 1 MB address space through 20-bit physical addresses. Immediate instructions carry data inside the instruction, while register instructions name CPU registers. AC and CY watch carries across different bit boundaries, and SP marks the stack top.

Use CS Fundamentals for Placements by Sanchit Sir when you need to rebuild processor and programming fundamentals. For general fetch-decode-execute flow, instruction formats and RISC/CISC design, continue with Instruction Set Architecture MCQs: 12 Solved ISA Design Questions; the calculations above remain specific to the 8085 and 8086.