Saying “DMA is faster” will not solve an I/O numerical. GATE asks how many bus cycles the controller steals, how much CPU time an interrupt service routine consumes, or why polling keeps the processor busy.
All three questions become manageable when you track two things: who moves each unit of data, and who owns the bus at that moment.
1. The three I/O transfer methods in one line each
The device and memory are the endpoints, but the CPU's role changes with the transfer method.
Programmed I/O: the CPU repeatedly checks device status and moves each data unit through a CPU register. While busy-waiting, it cannot use that time for another program.
Interrupt-driven I/O: the CPU does other work until the device interrupts it. The interrupt service routine, or ISR, handles each ready event and usually moves the data unit.
DMA: a Direct Memory Access controller moves a block directly between the device and main memory. The CPU sets up the address, direction and count, then normally receives one completion interrupt for the block.
“Direct” does not mean the transfer avoids the system bus. It means the CPU does not execute a load-and-store sequence for every byte or word. The DMA controller still needs bus access to reach memory.
This is also where I/O addressing enters the syllabus. Addressing Modes and Instruction Formats helps connect the data-transfer mechanism with how the processor names operands and I/O locations.
2. The single idea behind every numerical: who holds the bus
Treat a bus cycle as the accounting unit. If one bus cycle moves w bytes and the device produces R bytes per second, the required bus-cycle rate is:
Required bus cycles per second = R/w
If the bus supplies B cycles per second, the fraction consumed by the transfer is:
Bus fraction used = (R/w)/B
In cycle-stealing DMA, the controller takes individual cycles from the CPU. The processor stalls on those contested cycles and continues on the others. In burst mode, the DMA controller holds the bus for a sequence of transfers, so the CPU can be blocked from memory for the burst.
Do not assume that a bus clock and a CPU clock are always identical. A question may supply separate rates. Use the bus rate when counting bus cycles, and use the CPU rate when converting ISR cycles into CPU time.
3. Worked example: DMA cycle stealing and the 5% result
Suppose a device transfers at 20 MB/s. The DMA controller moves one 4-byte word per bus cycle, and the bus runs at 100 MHz.
Use decimal rate prefixes as stated in the question:
20 MB/s = 20 x 10^6 bytes/s
100 MHz = 100 x 10^6 = 10^8 bus cycles/s
The 100 MHz bus has a cycle time of:
1/(100 x 10^6) s = 10 ns
Now find how many cycles the device needs:
DMA cycles/s = (20 x 10^6 bytes/s) / (4 bytes/cycle)
DMA cycles/s = 5 x 10^6 cycles/s
Divide that demand by the available bus-cycle rate:
Fraction stolen = (5 x 10^6) / (10^8) = 0.05
Percentage stolen = 0.05 x 100 = 5%
The same result appears through a time check. Five million stolen cycles, each 10 ns long, occupy:
5 x 10^6 x 10 x 10^-9 s = 0.05 s per second
That is 5% of bus time. Under the simplified model in which each stolen cycle displaces a cycle the CPU could use, 95% remains for the CPU. The processor is slowed during the transfer, not halted for the full second.
4. Worked example: interrupt overhead versus programmed I/O
Now consider a slow device that delivers one byte every 50 microseconds. Servicing one byte costs 100 CPU cycles on a 1 GHz processor.
First convert the arrival interval to a rate:
50 microseconds = 50 x 10^-6 s
Bytes/s = 1/(50 x 10^-6) = 20,000 bytes/s
That is 20 kB/s with decimal prefixes.
At 1 GHz, one CPU cycle is 1 ns:
ISR time per byte = 100 cycles x 1 ns/cycle = 100 ns
Compare the ISR time with the 50 microsecond interval. Put both in nanoseconds:
50 microseconds = 50,000 ns
CPU fraction for ISR = 100/50,000 = 0.002
CPU percentage for ISR = 0.002 x 100 = 0.2%
An independent one-second check gives the same answer:
20,000 interrupts/s x 100 cycles/interrupt = 2,000,000 CPU cycles/s
2 x 10^6 / 10^9 = 0.002 = 0.2%
The CPU is therefore available for non-I/O work for about 99.8% of the time, ignoring other overheads not supplied in the question.
With programmed I/O, the CPU continuously polls for the entire 50 microsecond gap. It spends 100% of that interval in the busy-wait loop. There is no interrupt-entry cost, but removing interrupt overhead does not make polling free. It replaces a 100 ns ISR with 50,000 ns of occupied CPU time in this model.
5. Traps GATE plants in I/O numericals
Bits and bytes: divide a rate in bits per second by 8 before using a bytes-per-cycle transfer size.
Words and bytes: if one bus cycle moves a 4-byte word, divide the byte rate by 4. Do not treat each byte as a separate cycle.
Bus rate and CPU rate: DMA occupancy uses the bus cycle rate. ISR duration uses the CPU cycle rate.
Cycle stealing and burst mode: cycle stealing interleaves individual DMA cycles with CPU activity. Burst mode holds the bus for a run of cycles.
Interrupt count: interrupt-driven I/O may interrupt per byte or word as stated. Block DMA normally generates one completion interrupt, not one interrupt per byte.
Polling cost: programmed I/O can have zero interrupt overhead and still consume all CPU time in the busy-wait loop.
Cache and memory behaviour can limit how useful the remaining CPU cycles are. The surrounding hierarchy and hit-ratio arithmetic are covered in Cache Memory Mapping and Hit Ratio.
6. How GATE tests DMA, interrupts and programmed I/O
Common questions ask for the percentage of cycles stolen, effective CPU availability, maximum sustainable device rate, number of interrupts for a block, or CPU utilisation under polling and interrupts. A maximum-rate question is simply the same equation reversed:
Maximum data rate = usable bus cycles/s x bytes/bus cycle
More than 1,700 published Computer Organization questions in the KnowledgeGate bank cover DMA cycle stealing and interrupt-overhead patterns. For current subject weightage and paper details, use the official GATE portal. The rate conversions and utilisation methods remain the same.
7. Short version and next step
Programmed I/O keeps the CPU inside the transfer loop. Interrupt-driven I/O charges the CPU once per ready event. DMA moves the block and charges bus cycles, with the CPU mainly involved at setup and completion.
For each numerical, write the data rate, bytes moved per bus cycle, bus rate, interrupt frequency and ISR cycles with units. Then practise a timed Computer Organization set in the GATE Test Series, strengthen the concept sequence with GATE Guidance by Sanchit Sir, and use the GATE preparation category to move into the rest of I/O Organisation.
