Hierarchy & Locality MCQs: 12 Solved Questions with Explanations

Memory hierarchy questions look like simple recall until one option reverses speed, size, cost per bit, or access frequency. Locality questions can be even less obvious because the idea may be hidden inside cache block size, hit ratio, or average access time wording. The 12 solved questions below come from GATE, NIMCET, CDAC CCAT, and recruitment papers such as BEL, IBPS, and DSSSB, and they fit naturally into GATE CS Exam Preparation Courses & Test Series when you are revising Computer Organization.

Hierarchy and locality MCQs: how to use this set

Answer each question before reading its explanation. For every miss, record one error type: hierarchy order, trend direction, locality type, or AMAT arithmetic. That label tells you what to revise instead of merely memorising an option. Q4, Q6, Q7, and Q12 have full worked solutions. For more practice on the rest, work through the Computer Architecture learn module.

Memory hierarchy order, components, and trends

Q1. Fastest CPU-accessible memory (NIMCET 2021)

Which of the following is the fastest means of memory access for CPU?

• (A) Registers

• (B) Cache

• (C) Main memory

• (D) Stack

Answer: (A) Registers. Registers sit inside the processor's execution path and come before cache and main memory in the hierarchy. Cache is the strongest distractor because it is fast, but it is still below registers. A stack is an abstract organisation that may use registers or memory, not a faster physical memory level.

Q2. Fastest-to-slowest hierarchy (CDAC CCAT 2025)

Order the memory hierarchy from fastest to slowest:

• (A) Registers → Cache → Main memory → Disk

• (B) Cache → Registers → Main memory → Disk

• (C) Disk → Main memory → Cache → Registers

• (D) Main memory → Cache → Registers → Disk

Answer: (A) Registers → Cache → Main memory → Disk. Speed generally falls and capacity rises as you move through that order. Option (B) is the main trap: cache is fast, but registers remain faster and closer to CPU execution.

Q3. What does not increase down the hierarchy? (BEL 2023)

According to memory hierarchy as one goes down the hierarchy what will NOT occur?

• (A) Increasing capacity

• (B) Decreasing cost per bit

• (C) Increasing access time

• (D) Increasing frequency of access of the memory by the processor

Answer: (D) Increasing frequency of access of the memory by the processor. Downward movement means greater capacity, lower cost per bit, longer access time, and lower processor access frequency. Option (C) is easy to misread because increasing access time means slower access, not better performance.

Q4. Which item is not memory (GATE 2002 worked solution)

Which of the following is not a form of memory?

• (A) instruction cache

• (B) instruction register

• (C) instruction opcode

• (D) translation lookaside buffer

Answer: (C) instruction opcode. An opcode is the operation field encoded inside an instruction, so it is information rather than a storage structure. The instruction cache, instruction register, and translation lookaside buffer all hold information, despite serving different purposes.

Locality of reference and why cache works

Temporal locality means that a recently accessed item is likely to be used again. Spatial locality means that addresses near a recent access are likely to be used soon. Memory Hierarchy and Virtual Memory Explained expands this idea beyond cache to the wider storage hierarchy.

Q5. Why cache becomes effective (NIMCET 2021)

The Cache Memory is more effective because of

• (A) Memory localization

• (B) Locality of reference

• (C) Memory size

• (D) None of the mentioned

Answer: (B) Locality of reference. Programs tend to reuse recent instructions and data and then touch nearby addresses, allowing a small cache to serve many accesses. Option (A), “Memory localization”, resembles the correct phrase but is not the established principle being tested.

Q6. What locality justifies (GATE 1995 worked solution)

The principle of locality justifies the use of:

• (A) Interrupts

• (B) DMA

• (C) Polling

• (D) Cache Memory

Answer: (D) Cache Memory. Locality makes it useful to keep a small working set close to the CPU. Interrupts, DMA, and polling are I/O or control mechanisms, not storage structures whose effectiveness follows from locality.

Q7. Why a cache block contains multiple words (GATE 2001 worked solution)

More than one word is put in one cache block to

• (A) exploit the temporal locality of reference in a program

• (B) exploit the spatial locality of reference in a program

• (C) reduce the miss penalty

• (D) none of the above

Answer: (B) exploit the spatial locality of reference in a program. If a miss on word address 100 brings words 100, 101, 102, and 103, a later access to 101 can hit because it is nearby. Option (A) instead describes temporal locality, which would be demonstrated by accessing word 100 again.

Cache hits and average memory access time

Hit ratio is cache hits divided by total lookups. The calculations use the weighted cache-or-memory convention implied by their options. Cache Memory: Mapping and Hit Ratio gives the fuller treatment.

Q8. What happens on a cache hit? (IBPS 2023)

What happens during a cache hit in a computer system?

• (A) Data is transferred directly to the hard drive

• (B) Data is fetched from main memory into the cache

• (C) Requested data is retrieved directly from the cache memory

• (D) Data is permanently stored in the cache

• (E) The cache memory is cleared

Answer: (C) Requested data is retrieved directly from the cache memory. A hit means the requested data is already there. Option (B) describes a miss refill from a lower level.

Q9. Compute AMAT from hit ratio (TPSC 2026)

The access time of cache memory is 10 ns and that of main memory is 100 ns. If the hit ratio is 0.9, what is the average memory access time?

• (A) 19 ns

• (B) 28 ns

• (C) 55 ns

• (D) 90 ns

Answer: (A) 19 ns. Under the weighted convention:

Tavg = hTc + (1 - h)Tm = 0.9 × 10 + 0.1 × 100 = 9 + 10 = 19 ns

A sequential-lookup problem would add cache time before a main-memory miss and use a different expression. Always name the convention.

Q10. Recover hit ratio from AMAT (UPLT 2026)

If average access time of CPU is 20 ns, access time of main memory is 110 ns and the cache access time is 10 ns. What is the hit ratio?

• (A) 80%

• (B) 95%

• (C) 90%

• (D) 100%

Answer: (C) 90%. Using the same weighted convention:

20 = 10h + 110(1 - h) = 110 - 100h

Thus, 100h = 90, so h = 0.9 = 90%. Check: 0.9 × 10 + 0.1 × 110 = 9 + 11 = 20 ns.

Cache levels and block-size trade-offs

Upper cache levels trade capacity for speed. Larger blocks may capture more spatial locality, while smaller blocks transfer less data on a miss.

Q11. Relative size of L1, L2, and L3 (DSSSB 2018)

With respect to size, which of the following represents the correct relationships between different categories of cache memory?

• (A) L1 < L2 < L3

• (B) L1 < L3 < L2

• (C) L2 < L1 < L3

• (D) L3 < L2 < L1

Answer: (A) L1 < L2 < L3. L1 is smallest and closest, followed by the larger L2 and L3. Speed generally reverses towards L3, so option (D) confuses size with speed.

Q12. Smaller cache blocks and miss penalty (GATE 2014 worked solution)

In designing a computer’s cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context?

• (A) A smaller block size implies better spatial locality

• (B) A smaller block size implies a smaller cache tag and hence lower cache tag overhead

• (C) A smaller block size implies a larger cache tag and hence lower cache hit time

• (D) A smaller block size incurs a lower cache miss penalty

Answer: (D) A smaller block size incurs a lower cache miss penalty. At equal lower-memory bandwidth, a 16-byte block transfers one quarter as much data as a 64-byte block, reducing the transfer component. The trade-off is less captured spatial locality and four times as many entries in a fixed-capacity cache. Options (B) and (C) mishandle tag overhead.

Hierarchy and locality traps these exams repeat

Most one-line hierarchy questions reduce to one of four cues; recall the paired fact and the option picks itself.

Two numerical traps deserve a final check. Longer access time means lower speed, and an AMAT formula needs its weighted or sequential convention. Q9 recomputes to 9 + 10 = 19 ns; Q10 gives h = 0.9, with substitution returning 20 ns.

The short version and next step

Recall four facts cold: registers are fastest, lower hierarchy levels are generally larger and slower, locality makes a small cache effective, and AMAT answers depend on the convention stated or implied. Attempt only your missed questions again after one day, without looking at the marked answers, and check whether the error label has disappeared. GATE Guidance by Sanchit Sir provides a structured route through the complete COA sequence.