ISA questions mix three levels that students often revise separately: the instruction cycle, instruction-field arithmetic, and processor design choices such as RISC versus CISC. Twelve questions here cross all three, from the ordering of fetch, decode and execute to an 8/8/16-bit format that fixes both the register count and the memory size. Attempt each one before reading its explanation. Attributions run from GATE 1999 to Bihar STET 2025, taking in UGC NET, KVS, NVS, UPPSC and BPSC papers. For the wider Computer Architecture route, the GATE CS Exam Preparation Courses & Test Series page carries the courses and the test series.
1. ISA design map: instruction format, cycle and addressing modes
Keep these layers separate:
Layer | What it tells you |
|---|---|
Instruction format | Bits carrying the opcode and operands |
Addressing mode | Method for obtaining an operand or effective address |
Instruction cycle | CPU steps for the encoded instruction |
Design family | Typical RISC/CISC choices about instruction count, regularity, addressing modes, registers, and control |
Take 32-bit ADD R3, R1, R2 at PC = 0x1000. Fetch puts it in the instruction register and advances by 4 bytes: 0x1000 + 0x4 = 0x1004. Decode reads ADD, R3, R1, and R2. With R1 = 7 and R2 = 5, execute gets 7 + 5 = 12 and stores R3 = 12. No indirect cycle is needed.
MOV R1, #5 embeds 5; LOAD R1, [0x2400] names a fixed address. Pointers need indirect access, A[i] needs base-plus-index, record fields need base-plus-displacement, and recursive locals need stack-relative or frame-relative access.
2. Fetch, decode and execute: Questions 1-4
Question 1, instruction-cycle phases
Stem: Which of the following may not definitely occur in an instruction cycle? (i) Fetch cycle (ii) Execution cycle (iii) Indirect cycle
A. (ii) and (iii)
B. (iii) only
C. (i) only
D. (i) and (ii)
Answer: B. (iii) only. Fetch obtains the instruction, and execution performs it. Direct, immediate, and register addressing need no indirect lookup, so ADD R3, R1, R2 skips that cycle.
Question 2, UGC NET 2022
Stem: The correct sequence in the fetch-execute cycle is:
A. Decode
B. Fetch
C. Execute
Choose the correct answer from the following:
A. A−B−C
B. B−C−A
C. C−B−A
D. B−A−C
Answer: D. B−A−C. Translate: B = Fetch, A = Decode, and C = Execute. Thus B−A−C means obtain, interpret, then perform.
Question 3, KVS 2018
Stem: Actions implementing an instruction's meaning are actually carried out by _____.
A. Instruction fetch
B. Instruction decode
C. Instruction execution
D. Instruction program
Answer: C. Instruction execution. Fetch moves the instruction, while decode interprets it. Execute performs the action, such as 7 + 5 producing R3 = 12.
Question 4, NVS 2017
Stem: Which cycle refers to the process where one instruction is fetched and executed?
A. Fetch cycle
B. Instruction cycle
C. Execute cycle
D. Decode cycle
Answer: B. Instruction cycle. It is the whole sequence for one instruction. Fetch and execute are stages within it, although architectures need not expose identical stages.
An instruction cycle follows one instruction. Pipelining in Computer Architecture Explained shows how stages from different instructions overlap to improve throughput.
3. Bus width and instruction-format arithmetic: Questions 5-6
Question 5, UPPSC Polytechnic Lecturer 2022
Stem: A data bus 16 bits wide is accessed ___ times to read an instruction of 128 bits.
A. 2
B. 4
C. 8
D. 7
Answer: C. 8. Compute 128 bits / 16 bits per access = 8 accesses. Check it backwards: 8 × 16 = 128, while 7 × 16 = 112 bits.
Question 6, NVS 2022
Stem:
Consider the following structure of a 2-address instruction in a machine:
opcode operand1 operand2
8 bits 8 bits 16 bits
If the first operand is in a general-purpose register and the second operand is in memory, which of the following statements about the machine is correct?A. There are 256 registers and memory size is 64 KB bytes
B. There are 8 instructions and 8 registers
C. There are 256 registers and 2^16 KB memory
D. There are 256 instructions and 2^16 KB memory
Answer: A. There are 256 registers and memory size is 64 KB bytes. The 8-bit register field gives 2^8 = 256 registers, and the 16-bit address field gives 2^16 = 65,536 byte addresses, which is 65,536 / 1,024 = 64 KB. Options C and D read that same 16-bit field as 2^16 KB, which would be 64 MB. D's 256 is a real count, the 256 patterns of an 8-bit opcode, but its memory figure is the part that fails. B misreads both widths, since 8 bits hold 256 values and not 8.
4. RISC and CISC design choices: Questions 7-9
Question 7, KVS 2017
Stem: The technology that stores only the essential instructions on a microprocessor chip and thus enhances its speed is referred to as :
A. MIMD
B. CISC
C. RISC
D. SIMD
Answer: C. RISC. The stem simplifies RISC as a smaller, regular set supporting simpler decoding. MIMD and SIMD are parallel execution models, not ISA complexity categories. RISC is not automatically faster in every workload.
Question 8, BPSC 2024
Stem: Which of the following is the full form of CISC?
A. Complex Instruction Sequential Compilation
B. Complex Instruction Set Computer
C. Computer Integrated Sequential Compiler
D. More than one of the above
E. None of the above
Answer: B. Complex Instruction Set Computer. Expand it word by word. The other choices substitute compilation or compiler terms, so they do not name the ISA family.
Question 9, GATE 1999
Stem: The main difference(s) between a CISC and a RISC processor is/are that a RISC processor typically: a) has fewer instructions b) has fewer addressing modes c) has more registers d) is easier to implement using hardwired control logic
A. a and b
B. b and c
C. a and d
D. a, b, c and d
Answer: D. a, b, c and d. RISC typically has fewer instructions, fewer addressing modes, more registers, and regular design suited to hardwired control. Typically marks tendencies, not universal laws.
5. Addressing modes and language features: Question 10
Question 10, GATE 1999
Stem: A certain processor supports only immediate and direct addressing modes. Which of the following programming language features cannot be implemented on this processor? a) Pointers b) Arrays c) Records d) Recursive procedures with local variables
A. Only a
B. a and b
C. c and d
D. a, b, c and d
Answer: D. a, b, c and d. A pointer needs indirect access to reach whatever it holds the address of. An array element A[i] with an index computed at run time needs base(A) + i × element_size, a record field needs base-plus-displacement, and each recursive call needs its own frame reached relative to the stack pointer. Immediate #5 and direct [0x2400] fix their operand at assembly time, so neither can express these run-time patterns.
6. IA-32 flags and the x86 starting point: Questions 11-12
Question 11, BPSC 2023
Stem: In IA-32 architecture along with the general flags, which of the following conditional flags is provided?
A. TF
B. IOPL
C. IF
D. More than one of the above
E. None of the above
Answer: D. More than one of the above. IA-32 provides all three: TF for single-step trapping, IF for maskable interrupts, and IOPL as an I/O privilege-level field, so more than one of the listed items really does sit in EFLAGS. Read the wording carefully, because those three are system flags rather than condition codes. The condition codes proper are CF, PF, AF, ZF, SF and OF, which reflect arithmetic or logical outcomes.
Question 12, Bihar STET 2025
Stem: In which year did Intel release the first x86 microprocessor, the 8086, which laid the foundation for the x86 architecture widely used in personal computers?
A. 1971
B. 1978
C. 1986
D. 1991
Answer: B. 1978. Intel released the 8086 in 1978, and the x86 name comes from that part and its successors. The other years belong to different chips: the 4004 dates from 1971, the 80386 from the mid-1980s, and the 486SX from 1991.
7. ISA MCQ traps, retrieval checklist and next practice step
Retrieve the method, not just the answer letter:
Questions | What to retrieve |
|---|---|
1-4 | Optional versus compulsory instruction-cycle phases |
5 | Transfer width versus instruction width |
6 | Field width versus number of encodable values |
7-9 | RISC/CISC terms and typical traits |
10 | Language feature versus required addressing mode |
11-12 | Condition flags versus control fields, then historical recall |
Six traps matter. Eight bits encode 2^8 = 256, not eight choices. Fetch is not the full cycle. SIMD and MIMD are not RISC/CISC alternatives. Keep typically in comparisons. TF, IF and IOPL are system flags, not condition codes. For Question 6, use 2^16 byte addresses to calculate the memory size.
Close the explanations and redo Questions 2, 5, 6, 9, and 10. Show B−A−C, 128 / 16 = 8, 2^8 = 256, 2^16 = 65,536, four RISC checks, and one addressing form per language feature.
Next, study Cache Memory: Mapping and Hit Ratio. For a structured GATE CS route, use GATE Guidance by Sanchit Sir; for an exam-specific alternative, use the ISRO Scientist/Engineer SC (CS) Course.
