Instruction Structure MCQs: 12 Solved Questions on Opcodes, Address Formats and Bit Allocation

Instruction-format questions reduce to three things: opcode space, operand fields, and the CPU organisation that decides how many operands an instruction has to name. Get those right and the rest is arithmetic. Count the operations to size the opcode, count the registers to size each operand field, and whatever bits are left over are the immediate.

Instruction Structure MCQs: opcode and format basics

An instruction word contains operation and operand fields, each consuming encoding space.

Question 1: opcode capacity from n bits

DSSSB 2021, PGT

Open this question in the Instruction Structure module

When n bits are used to represent an operation (op) code, then how many different operations a computer can perform?

• A. n operations

• B. 2 × n operations

• C. 2ⁿ operations

• D. n² operations

Answer: C. 2ⁿ operations

n binary positions have two choices each, giving 2 × 2 × ... × 2 = 2ⁿ patterns. For n = 3, the patterns are 000, 001, 010, 011, 100, 101, 110, and 111, giving eight operation codes.

Question 2: supported address-count formats

UGC NET 2013, June

Open this question in the Instruction Structure module

Computers can have instruction formats with

• A. only two address and three address instructions

• B. only one address and two address instructions

• C. only one address, two address and three address instructions

• D. zero address, one address, two address and three address instructions

Answer: D. zero address, one address, two address and three address instructions

Address count measures explicit operands, not participating values. Usual organisations are stack for zero-address, accumulator for one-address, destructive source and destination for two-address, and a separate destination plus two sources for three-address.

Question 3: instruction-format design criteria

UGC NET 2013, December

Open this question in the Instruction Structure module

Which of the following is a design criterion for instruction formats?

• A. The size of instructions

• B. The number of bits in the address fields

• C. The sufficient space in the instruction format to express all the operations desired

• D. All of these

Answer: D. All of these

Instruction length sets the bit budget; address and opcode widths limit operands and operations. Balancing all three makes every listed factor a design criterion.

Address-format MCQs: zero, one and three address instructions

Compare these forms:

• PUSH A; PUSH B; ADD illustrates zero-address stack execution.

• LOAD A; ADD B illustrates one-address accumulator execution.

• ADD R1, A, B illustrates a three-address form with a destination and two sources.

Question 4: classify an ADD instruction

DSSSB 2021, TGT Shift 5

Open this question in the Instruction Structure module

This instruction is of what type?

ADD R1, A, B

• A. Zero Address Instruction

• B. Two Address Instruction

• C. One Address Instruction

• D. Three Address Instruction

Answer: D. Three Address Instruction

R1, A, and B are three explicit address fields. R1 receives the result while A and B supply the operands, so this is a three-address instruction.

Question 5: zero-address organisation

UPPSC Polytechnic Lecturer 2018

Open this question in the Instruction Structure module

Zero address instructions are implemented with the help of:

• A. Queue

• B. Stack

• C. Register

• D. None of the above

Answer: B. Stack

Zero-address arithmetic takes operands implicitly from the stack. PUSH 10; PUSH 30; ADD removes 30 and 10, adds them, and pushes 40.

Question 6: the implied accumulator

DSSSB 2024, TGT

Open this question in the Instruction Structure module

Which of the following instruction formats uses an implied accumulator (AC) register for all data manipulation?

• A. One-address instructions

• B. Three-address instructions

• C. Zero-address instructions

• D. Two-address instructions

Answer: A. One-address instructions

A one-address instruction names one memory operand while the accumulator is the implicit second operand and result register. After LOAD A, for example, ADD B means AC <- AC + M[B].

Question 7: accumulator and stack statements

DSSSB 2018

Open this question in the Instruction Structure module

State whether the following statements are true or false.
(i) With one-address instructions, the programmer generally has available only one general-purpose register, the accumulator.
(ii) Zero-address instructions are applicable to a special memory organization called a stack.

• A. (i) True, (ii) True

• B. (i) True, (ii) False

• C. (i) False, (ii) True

• D. (i) False, (ii) False

Answer: A. (i) True, (ii) True

One-address arithmetic uses the accumulator; zero-address arithmetic takes operands from the stack and returns the result.

One-address instruction MCQs: translate expressions into accumulator code

Every arithmetic instruction uses the accumulator implicitly. Use STORE T only to preserve a value while computing another subexpression.

Question 8: count the one-address instructions

Indian Space Research Organization 2015

Open this question in the Instruction Structure module

In X = (M + N x O)/(P x Q), how many one-address instructions are required to evaluate it?

• A. 4

• B. 6

• C. 8

• D. 10

Answer: C. 8

LOAD P
MUL Q
STORE T
LOAD N
MUL O
ADD M
DIV T
STORE X

The first three instructions preserve P × Q in T; the next three calculate numerator N × O + M. The final two divide by T and store the answer, so 3 + 3 + 2 = 8.

Question 9: choose the correct accumulator sequence

DSSSB 2018

Open this question in the Instruction Structure module

Which sequence of one-address, accumulator-based instructions can be used to evaluate Y = (A - B) / (C + D * E)?

A. LOAD D
   MPY E
   ADD C
   STORE Y
   LOAD A
   SUB B
   DIV Y
   STORE Y

B. LOAD D
   MPY E
   ADD C
   LOAD A
   STORE Y
   SUB B
   DIV Y
   STORE Y

C. LOAD D
   ADD C
   MPY E
   STORE Y
   LOAD A
   SUB B
   DIV Y
   STORE Y

D. LOAD D
   MPY E
   ADD C
   STORE Y
   LOAD A
   DIV Y
   SUB B
   STORE Y

Answer: A

Option A forms denominator C + D × E with LOAD D; MPY E; ADD C, then preserves it with STORE Y. LOAD A; SUB B forms the numerator, and DIV Y; STORE Y stores the quotient. Other sequences reorder operations or overwrite the denominator.

Instruction-encoding numericals: opcode, register and immediate fields

Use the same three-step method each time:

1. Use ceil(log2 K) bits to represent K choices.

2. Subtract fixed fields from the instruction length.

3. Interpret the remaining bits according to how many operand fields share them.

Question 10: infer the number of registers from a 32-bit format

Indian Space Research Organization 2020

Open this question in the Instruction Structure module

Consider a 32-bit processor which supports 70 instructions. Each instruction is 32 bit long and has 4 fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is 8191. How many registers does the processor have?

• A. 32

• B. 64

• C. 128

• D. 16

Answer: B. 64

Seventy operations need ceil(log2 70) = 7 opcode bits. Unsigned values from 0 through 8191 need 13 bits because 2^13 = 8192. Register identifiers share 32 - 7 - 13 = 12 bits; each gets 12 / 2 = 6 bits and selects 2^6 = 64 registers. The layout is 7 opcode | 6 register | 6 register | 13 immediate = 32 bits.

Question 11: maximise a variable-size opcode class

GATE 2018

Open this question in the Instruction Structure module

A processor has 16 integer registers (R0, R1, .. , R15) and 64 floating point registers (F0, F1,… , F63). It uses a 2-byte instruction format. There are four categories of instructions: Type-1, Type-2, Type-3, and Type-4. Type-1 category consists of four instructions, each with 3 integer register operands (3Rs). Type-2 category consists of eight instructions, each with 2 floating point register operands (2Fs). Type-3 category consists of fourteen instructions, each with one integer register operand and one floating point register operand (1R+1F). Type-4 category consists of N instructions, each with a floating point register operand (1F).
The maximum value of N is __________.

GATE asks this as a numerical answer type question: there are no options, you type the value of N into the answer box.

Answer: 32

2^16 = 65,536 encodings are available. Type-1 uses 4 × 16^3 = 16,384, Type-2 uses 8 × 64^2 = 32,768, and Type-3 uses 14 × 16 × 64 = 14,336. Their 16,384 + 32,768 + 14,336 = 63,488 total leaves 65,536 - 63,488 = 2,048. Each Type-4 instruction needs 64 encodings, so N = 2,048 / 64 = 32.

Question 12: maximise the immediate field

GATE 2025, Set 1

Open this question in the Instruction Structure module

A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instruction?

ADD R1, #25           // R1 = R1 + 25

• A. 16

• B. 20

• C. 22

• D. 24

Answer: B. 20

ceil(log2 50) = 6 opcode bits, and log2 64 = 6 register bits. Thus 32 - 6 - 6 = 20 immediate bits. The layout is 6 opcode | 6 register | 20 immediate = 32 bits.

Instruction Structure MCQs: how exams move from recall to calculation

The split runs roughly along paper lines. Questions 1 to 7 are from DSSSB, UGC NET and UPPSC papers, and each one is settled by recognising a form: count the operands the instruction names explicitly, and the organisation follows from that count. Questions 8 to 12 ask you to produce something instead. Questions 8 and 9 want the accumulator sequence written out instruction by instruction. Questions 10, 11 and 12, all ISRO or GATE, want a bit budget that adds up exactly to the instruction length, with nothing spare and nothing missing. So the working order is fixed: settle the address count first, allocate the opcode and operand fields next, and read whatever bits remain as the immediate.

Continue with Pipelining in Computer Architecture: Speedup and Hazards for what happens to these instructions once they are fetched, and Addressing Modes and Instruction Formats MCQs for the other half of this topic, where the operand field is decoded into an effective address.

Instruction Structure MCQs: the short version and next step

• n opcode bits give 2ⁿ operations.

• Zero-address means stack.

• One-address means accumulator.

• Total instruction bits equal opcode bits plus operand-field bits.

Redo Questions 8, 10, and 11 without the explanations. They test code generation, fixed-field allocation, and encoding-space allocation.

For GATE-level COA, use GATE Guidance by Sanchit Sir alongside GATE CS Exam Preparation. For placement-focused revision, choose CS Fundamentals for Placements by Sanchit Sir.