CPU Organization Basics MCQs: 12 Solved Questions with Explanations

CPU basics can look like a list of short forms, but the questions make you follow an instruction through the control unit, registers, ALU, buses and memory while keeping frequency and capacity units separate. Here are 12 solved published questions, including three worked numericals. Answer each before reading its explanation. Use the GATE CS preparation courses and test series for structured study.

CPU organisation in one instruction trace

Use this model: CPU = control unit + ALU + registers. Buses connect it to memory and I/O. A computer system contains CPU, memory and I/O, so ALU and control unit are CPU parts, not peer system-level components.

PC points to the next instruction. MAR carries a memory address, MDR buffers a value in transit, and IR holds the current instruction. The control unit issues signals, while the ALU performs arithmetic and logic.

In a fictional 32-bit teaching CPU, PC = 0x0040; memory there holds the 4-byte instruction ADD R1, R2; R1 = 9; and R2 = 6.

1. Fetch copies 0x0040 from PC to MAR. The encoded instruction travels through MDR into IR, and PC advances to 0x0044.

2. Decode selects R1 and R2.

3. Execute sends 9 and 6 to the ALU, which calculates 9 + 6 = 15.

4. Write-back stores 15 in R1.

These are teaching values, not bank data or an exam-specific architecture. Remember: hertz means cycles per second; a 32-bit register or bus carries 32 bits; 2^s sources need s selector bits; and a address lines distinguish 2^a word addresses.

Clock speed and the CPU's core units: Questions 1-4

Question 1, IISC 2021

The computer speed is measured in

0. Kilobyte
1. Bites
2. Hertz
3. Megabyte

Answer: C. Hertz

Hertz means cycles per second, so it is the relevant unit for clock frequency. Kilobyte and megabyte measure data quantity, while Bites is not the required computing unit. Clock frequency alone does not determine CPU performance. Instruction count, cycles per instruction and memory delays also matter, and one instruction need not finish in one cycle.

Question 2, BPSC 2023

The three main components of a digital computer system are

0. memory, I/O, DMA
1. ALU, CPU, memory
2. memory, CPU, I/O
3. More than one of the above
4. None of the above

Answer: C. memory, CPU, I/O

Memory stores instructions and data, the CPU processes them and controls operations, and I/O connects the system to external devices. DMA is a transfer mechanism or controller. The ALU is already a subunit of the CPU, so the other lists mix different levels of the system hierarchy.

Question 3, HTET 2023

All the calculations and decision making operations are performed in which unit?

0. Control Unit
1. Algorithm Unit
2. Arithmetic Logical Unit
3. Memory Unit

Answer: C. Arithmetic Logical Unit

In the teaching trace, the ALU receives 9 and 6 and adds them to obtain 15. It can also perform comparisons and bitwise logic. The control unit selects and sequences the operation, while memory stores values. The bank's wording is Arithmetic Logical Unit, so that exact offered answer is retained.

Question 4, TPSC 2025

What is the function of the Control Unit (CU) in a computer system ?

0. Execute instructions
1. Store data
2. Manage and coordinate the execution of instructions
3.  Perform input/output operations

Answer: C. Manage and coordinate the execution of instructions

The CU decodes an instruction and sends timing and control signals for register transfers, ALU actions, memory operations and I/O interactions. In the teaching trace, it coordinates every step from PC = 0x0040 through write-back. It is not long-term storage, and it does not replace the ALU that performs the addition.

Following an instruction through IR, PC and MAR: Questions 5-7

Use a quick diagnostic: the "instruction itself" points to IR, the "address of the next instruction" points to PC, and the "address used for a memory transfer" points to MAR. In our trace, these are IR = ADD R1, R2, PC = 0x0044 after fetch, and MAR = 0x0040 during fetch.

Question 5, BPSC 2023

The register that contains the instruction that is being executed is called ______.

0. accumulator
1. program counter
2. instruction register
3. More than one of the above
4. None of the above

Answer: C. instruction register

IR holds the current encoded instruction during decode and execution. In the trace it holds ADD R1, R2. PC already points ahead to 0x0044, while an accumulator holds ALU operands or results in an accumulator-style CPU.

Question 6, DSSSB 2022

Which of the following registers of a CPU stores the address of the next instruction to be executed?

0. IR
1. MAR
2. AC
3. PC

Answer: D. PC

Before fetching the 4-byte instruction, PC = 0x0040. The next sequential address is 0x0040 + 4 = 0x0044, so PC becomes 0x0044 after fetch. A branch or jump can replace that sequential value, but PC still identifies the address from which the next instruction will be fetched.

Question 7, BPSC 2023

The register which holds the address of location of memory to and from which data are to be transferred is known as ______.

0. index register
1. memory address register
2. memory buffer register
3. More than one of the above
4. None of the above

Answer: B. memory address register

MAR holds an address, not its contents. During the example fetch, MAR contains 0x0040, while MDR carries the instruction bits stored there. For a later read from address 0x01A0, MAR would hold 0x01A0 and MDR would hold the returned value.

MDR and accumulator: Questions 8-9

MDR is the memory-boundary register for bits in transit. An accumulator is a working register used in many designs for ALU operands and results, but it is not compulsory in every modern ISA.

Question 8, RSSB 2023

The instructions or data fetched from the memory, is stored in the ____ to decode and execute.

0. MAR
1. MDR
2. PC
3. ROM
4. Question not attempted

Answer: B. MDR

MDR is the intended offered answer because it buffers bits fetched from memory. For an instruction fetch, those bits normally move from MDR into IR before decode and execution. This distinction reconciles the stem with Question 5: MDR handles the transfer across the memory boundary, while IR holds the current instruction.

Question 9, UP Police 2016

Which of the following CPU registers is used to store values for ALU operations?

0. Accumulator
1. Program counter
2. Index register
3. Instruction register

Answer: A. Accumulator

In the accumulator-style CPU model used by this item, start with AC = 9, add operand 6, and finish with AC = 9 + 6 = 15. PC tracks instruction addresses, an index register assists address calculation, and IR holds the current instruction.

Selecting one of 16 registers onto a common bus: Question 10

Question 10, UPPSC Polytechnic Lecturer 2022

A digital computer has a common bus system for 16 registers of 32 bits each. Bus is constructed with multiplexers. The number of selection inputs in each multiplexer is ______.

0. 8
1. 5
2. 4
3. None of the above

Answer: C. 4

Let s be the number of selector inputs. They must encode 16 choices:

2^s = 16

s = log2(16) = 4

The 32-bit bus requires 32 parallel 16-to-1 multiplexers, one per bit position, but all share the same four selector inputs. Do not answer 32 from the bus width or 16 from the source count.

When the control unit asserts 0110, all 32 bits of R6 appear on the bus. This is a teaching expansion of the bank numbers.

Address lines, data lines and clock period: Questions 11-12

Start with units: memory depth determines address lines, word width determines data lines, and frequency is the reciprocal of period. Review number systems and base conversions if powers of two still slow you down.

Question 11, Coal India 2017

Consider a memory unit of size 96 K × 16, where the first component represents the total number of words and the second component represents the number of bits per word. What will be the number of address lines and input-output data lines?

0. 16 address lines, 7 data lines
1. 7 address lines, 16 data lines
2. 17 address lines, 16 data lines
3. 16 address lines, 17 data lines

Answer: C. 17 address lines, 16 data lines

First calculate the memory depth:

96 K = 96 x 1024 = 98,304 words

Now bracket that count with powers of two:

2^16 = 65,536 < 98,304

2^17 = 131,072 >= 98,304

Therefore, 17 address lines are required, with some addresses unused. A 16-bit word needs 16 input-output data lines. Address count and word width answer different questions. Apply this separation when dividing cache addresses into tag, index and offset fields.

Question 12, HPSC 2021

If a processor clock is rated as 1250 million cycles per second, then its clock period is

0. 1·9*10^-10 sec
1. 1·6*10^-9 sec
2. 1·25*10^-10 sec
3. 8*10^-10 sec
4. Question not attempted

Answer: D. 8*10^-10 sec

Convert the frequency before taking its reciprocal:

f = 1250 million cycles/s = 1.25 x 10^9 Hz

T = 1/f = 1/(1.25 x 10^9) s

T = 0.8 x 10^-9 s = 8 x 10^-10 s = 0.8 ns

Cross-check by multiplication:

(1.25 x 10^9)(8 x 10^-10) = 10 x 10^-1 = 1

The reciprocal returns one complete cycle, so the units and exponent are consistent.

Answer strip, traps and the next practice step

Answer strip: 1-C, 2-C, 3-C, 4-C, 5-C, 6-D, 7-B, 8-B, 9-A, 10-C, 11-C, 12-D.

Use this scorecard only as a study recommendation, not an official threshold:

• 10-12: Retry only the missed concepts after one day.

• 7-9: Redraw the instruction trace and recalculate the three numericals.

• 0-6: Rebuild the PC-MAR-MDR-IR path before attempting more MCQs.

Explain every answer without its letter. Avoid five traps: clock rate in bytes, ALU as a peer of CPU, PC swapped with IR, MAR's address confused with MDR's contents, and word width used to count address lines. Check clocks by multiplying frequency and period, and check memory with 2^(a-1) < locations <= 2^a.

Move from clock cycles to pipelining in computer architecture, where instructions overlap. For full-subject learning, use GATE Guidance by Sanchit Sir. For broader timed practice, move to the GATE Test Series.