Sequential circuits add memory to logic: the output now depends on the past, through latches, flip-flops, and the counters built from them. GATE tests this with flip-flop behaviour, excitation-table conversions, and counter analysis. Because so many sequential questions lean on a circuit diagram, this set deliberately favours items whose full setup is stated in words, and for the two circuit questions the wiring is restated faithfully so nothing is lost. Below are 11 solved MCQs from KnowledgeGate's published question bank, every one a previous-year GATE problem with the year marked. Attempt each before reading the explanation, which stays short on purpose. Every question here links its exact solved page; if a concept feels shaky, the full theory sits in the Digital Electronics learn module.
Latches and flip-flop behaviour
Q1. In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, the result is (GATE 2004)
(a) Q = 0, Q' = 1
(b) Q = 1, Q' = 0
(c) Q = 1, Q' = 1
(d) Indeterminate state
Answer: (c) Q = 1, Q' = 1. A NAND output goes high whenever any input is 0, so driving both S and R to 0 forces both gate outputs to 1. This is the forbidden or invalid state of the NAND latch, because Q and Q' should always be complements. Note that for a NAND latch the active level is 0, the mirror image of the NOR latch (see the solved page).
Q2. Which input sequence for a cross-coupled R-S flip-flop made from two NAND gates may lead to an oscillation? (GATE 2007)
(a) 11, 00
(b) 01, 10
(c) 10, 01
(d) 00, 11
Answer: (d) 00, 11. The pair 0,0 is the forbidden state that drives both outputs high. If the inputs then switch simultaneously to 1,1, both gates try to change at once, and with equal delays neither output settles, so the circuit can oscillate. This race condition is exactly why the 0,0 input is banned for a NAND latch (see the solved page).
Q3. A positive edge-triggered D flip-flop has its Q output wired to both the J and K inputs of a positive edge-triggered JK flip-flop, and the JK flip-flop's Q output is wired back to the D input. Initially the D flip-flop output is 1 and the JK output is 0. With J = K = 1 as toggle and J = K = 0 as hold, the sequence at the JK output (including the initial state) is (GATE 2015)
(a) 0110110...
(b) 0100100...
(c) 011101110...
(d) 011001100...
Answer: (a) 0110110... Trace by rising edges. The JK flip-flop toggles or holds according to J = K = D_old, while the D flip-flop copies the old JK output. Starting from D = 1, JK = 0 and stepping the clock gives the JK output 0, 1, 1, 0, 1, 1, 0, a repeating 0-1-1 block. Two interconnected flip-flops make a simple 3-state cycle (see the solved page).
Q4. A T flip-flop and a D flip-flop are cross-connected: the D flip-flop output feeds the T flip-flop input and the T flip-flop output feeds the D input. Both Q0 and Q1 start at 1 before the first clock. The outputs are (GATE 2017)
(a) Q1 Q0 = 11 after the 3rd cycle, 00 after the 4th
(b) Q1 Q0 = 11 after the 3rd cycle, 01 after the 4th
(c) Q1 Q0 = 00 after the 3rd cycle, 11 after the 4th
(d) Q1 Q0 = 01 after the 3rd cycle, 01 after the 4th
Answer: (b). The update rules are Q1_next = Q1 XOR Q0 (the toggling stage) and Q0_next = Q1 (the copy stage). Starting from Q1 Q0 = 11 the states run 11, then 01, 10, 11 after the third clock, then 01 after the fourth. Writing the next-state equations before tracing is what keeps flip-flop-interconnection questions from getting muddled (see the solved page).
Counters: Johnson, ripple and synchronous
Q5. A 4-bit Johnson counter starts at 0000. Its counting sequence is (GATE 2015)
(a) 0, 1, 3, 7, 15, 14, 12, 8, 0
(b) 0, 1, 3, 5, 7, 9, 11, 13, 15, 0
(c) 0, 2, 4, 6, 8, 10, 12, 14, 0
(d) 0, 8, 12, 14, 15, 7, 3, 1, 0
Answer: (d). A Johnson, or twisted-ring, counter feeds the inverted output of the last flip-flop back to the first and shifts on each clock. This grows a block of 1s from the top and then shrinks it, so a 4-bit version has 8 distinct states: 0, 8, 12, 14, 15, 7, 3, 1, and back to 0. An n-bit Johnson counter always has 2n states, versus n for a plain ring counter (see the solved page).
Q6. The minimum number of D flip-flops needed to design a mod-258 counter is (GATE 2011)
(a) 9
(b) 8
(c) 512
(d) 258
Answer: (a) 9. A counter with m distinct states needs the smallest n with 2^n at least m. Since 2^8 = 256 is below 258 and 2^9 = 512 clears it, 9 flip-flops are required, leaving 512 - 258 = 254 unused states. The flip-flop count grows with the logarithm of the modulus, not the modulus itself (see the solved page).
Q7. How many pulses change the contents of an 8-bit up counter from 10101100 to 00100111, with the rightmost bit as LSB? (GATE 2005)
(a) 134
(b) 133
(c) 124
(d) 123
Answer: (d) 123. Read the values as decimal: 10101100 is 172 and 00100111 is 39. An 8-bit up counter wraps at 256, so the pulse count is (39 - 172) mod 256, which is (-133) mod 256 = 123. Modular arithmetic handles the wraparound cleanly, no need to count step by step (see the solved page).
Q8. With k = 2^n, a circuit feeds the output of an n-bit binary counter into an n-to-2^n decoder. This circuit is equivalent to a (GATE 2014)
(a) k-bit binary up counter
(b) k-bit binary down counter
(c) k-bit ring counter
(d) k-bit Johnson counter
Answer: (c) k-bit ring counter. The binary counter steps through 0 to 2^n - 1, and the decoder turns each binary value into exactly one active output line. So on every clock a single 1 moves from one output to the next, which is precisely the one-hot rotation of a ring counter. Pairing a counter with a decoder is the standard way to synthesise a ring counter (see the solved page).
Excitation tables and state analysis
Q9. A 2-bit saturating up-counter has the next-state table below and is built from T flip-flops. The expressions for T1 and T0 are (GATE 2017)
present 00, next 01
present 01, next 10
present 10, next 11
present 11, next 11
(a) T1 = Q1.Q0, T0 = Q1'.Q0'
(b) T1 = Q1'.Q0, T0 = Q1' + Q0'
(c) T1 = Q1 + Q0, T0 = Q1'.Q0'
(d) T1 = Q1'.Q0, T0 = Q1 + Q0
Answer: (b) T1 = Q1'.Q0, T0 = Q1' + Q0'. For a T flip-flop the required input is T = Q XOR Q-next. Reading the table, Q1 must toggle only in state 01, so T1 = Q1'.Q0, and Q0 must toggle in every state except 11, so T0 = Q1' + Q0'. The excitation rule T = present XOR next is the backbone of every synchronous counter design (see the solved page).
Q10. A 3-bit counter built from T flip-flops (outputs P, Q, R) is wired so that TP = R, TQ = P', and TR = Q'. Starting from PQR = 000, the next three states are (GATE 2021)
(a) 011, 101, 000
(b) 001, 010, 111
(c) 011, 101, 111
(d) 001, 010, 000
Answer: (a) 011, 101, 000. Apply next = present XOR T at each step. From 000 the toggle inputs are (TP, TQ, TR) = (0, 1, 1), giving 011. From 011 they become (1, 1, 0), giving 101. From 101 they are (1, 0, 1), giving 000. Feeding the current outputs through the toggle equations one clock at a time is the whole method for counter analysis (see the solved page).
Q11. A 1-input, 2-output synchronous circuit outputs 00 until the count of 0s exceeds the count of 1s by 2 (then it outputs 10 forever) or the count of 1s exceeds the count of 0s by 2 (then it outputs 01 forever). The minimum number of states needed is (GATE 2003)
(a) 5
(b) 6
(c) 7
(d) 8
Answer: (a) 5. Track the running difference d between the number of 0s and 1s. Before a decision is reached, d can only be -1, 0, or +1, needing three states, all emitting 00. Once d hits +2 or -2 the machine enters one of two absorbing states that lock the output, adding two more, for five in total. Modelling the essential memory, not the raw input, is what keeps the state count minimal (see the solved page).
How this set is examined
The 11 questions above trace the sequential story end to end: latch and flip-flop behaviour including the forbidden states (Q1 to Q4), the counter families of Johnson, ripple and synchronous (Q5 to Q8), and the excitation-table method that turns a desired sequence into flip-flop inputs (Q9 to Q11). The single most useful habit is to write the next-state equations first and only then trace the clock. This is a figure-heavy topic, so if a diagram-based PYQ stumps you, rebuild the theory before forcing the picture. The same analysis style feeds back into the Combinational circuits MCQs, whose adders and MUXes are the building blocks inside these counters.
If the flip-flop conversions still feel slow, the full theory with worked timing sits in our Sequential circuits: flip-flops and counters deep dive. GATE aspirants get the full digital electronics sequence inside GATE Guidance by Sanchit Sir, and you can place the subject in the wider syllabus on the GATE CS Exam page. Solve, review the ones you missed, and come back a week later; the second pass is where the marks get locked in.
