In an SR latch made by cross-coupling two NAND gates, if both S and R inputs…

Concept: A NAND gate outputs 0 only when ALL of its inputs are 1; it outputs 1 the moment ANY single input is 0, regardless of its other input. In a cross-coupled NAND latch, one gate produces Q from inputs (S, Q') and the other produces Q' from inputs (R, Q) — each output feeds back as an input to the other gate.

Application:

1. S = 0 is one input to the gate that produces Q, so that gate's output is forced to 1 regardless of the Q' feedback it is receiving — giving Q = 1.

2. R = 0 is one input to the gate that produces Q', so that gate's output is forced to 1 regardless of the Q feedback it is receiving — giving Q' = 1.

Cross-check: Cross-check against the latch's normal behaviour: S = 0 with R = 1 gives the SET state (Q = 1, Q' = 0), and S = 1 with R = 0 gives the RESET state (Q = 0, Q' = 1) — in both, Q and Q' stay complementary. Driving S = 0 and R = 0 together breaks that complementary pattern, since both outputs are forced high at once. This is exactly why the combination is treated as forbidden: it is fully determinate while held, but if S and R are released back to 1 at the same instant, a propagation-delay race between the two gates decides which output falls first, making the resulting stored state unpredictable.

Result: Q = 1, Q' = 1 — the forbidden/invalid input state of the NAND-based SR latch (the official answer for this GATE 2004 CS question).