Students may remember XOR yet confuse carry with borrow, half with full circuits, and one-bit formulas with multi-bit delay. The 12 questions below, most of them previous-year questions from ISRO, GATE, UGC NET, DSSSB, BPSC, TPSC and BEL, punish exactly those confusions, and every answer works through the one step that settles it. Attempt a question before you read its answer.
Adders and subtractors formula sheet: sum, carry, difference and borrow
Circuit | Output bit | Carry or borrow output |
|---|---|---|
Half adder |
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Full adder |
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Half subtractor |
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Full subtractor |
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A' means NOT A. Carry is addition overflow; borrow comes from the next higher bit during subtraction.
At A = 0, B = 1, both circuits give 0 ⊕ 1 = 1. Yet the half adder has C = 0 × 1 = 0, while the half subtractor has Bₒᵤₜ = 1 × 1 = 1. Same XOR, different signal. Use the Boolean Algebra and K-map Minimization Guide if needed.
Half-adder and full-adder basics: Questions 1-4
Question 1, BPSC 2024
In a half-adder circuit, what are the outputs?
A. Sum and Carry
B. Difference and Borrow
C. Sum and Difference
D. More than one of the above
E. None of the above
Answer: A. A half adder returns low-order Sum and high-order Carry. Since 1 + 1 = 10₂, S = 0, C = 1; difference and borrow are subtraction outputs.
Question 2, TPSC 2025
Logic gates required to built up a half adder circuit are :
A. EX-OR gate and NOR gate
B. EX-OR gate and AND gate
C. EX-OR gate and OR gate
D. EX-NOR gate and NAND gate
Answer: B. XOR gives S = A ⊕ B; AND gives C = AB. For 00, 01, 10, 11, Sum is 0, 1, 1, 0 and Carry is 0, 0, 0, 1, confirming both gates.
Question 3, TPSC 2025
The sum output of a full adder is given by which Boolean expression ?
A. A + B
B. A ⊕ B
C. A · B
D. (A ⊕ B) ⊕ C_in
Answer: D. Sum is the parity of A, B and incoming C_in. At 1, 1, 1, it is 1 ⊕ 1 ⊕ 1 = 1; formulas omitting C_in fail.
Question 4, BEL 2023
Which of the following pair is CORRECT?
I. Half adder - A combinational circuit that performs the addition of two bits
II. Full adder - A combinational circuit that performs the addition of three bits
A. Neither I nor II
B. Only II
C. Only I
D. Both I and II
Answer: D. Statement I defines a half adder. Statement II means two operand bits plus C_in, not three multi-bit operands, so both are correct.
Full-adder outputs and gate structure: Questions 5-6
Question 5, TPSC 2024
Which gate combination is used to generate the sum and carry outputs in a full adder circuit?
A. XOR of inputs for sum; AND only for carry.
B. AND of inputs for sum; XOR, OR, and AND for carry.
C. XOR of inputs for sum; XOR, AND, and OR for carry.
D. OR of inputs for sum; XOR, AND, and OR for carry.
Answer: C. Build P = A ⊕ B, S = P ⊕ Cᵢₙ, C₁ = AB, C₂ = PCᵢₙ, and Cₒᵤₜ = C₁ + C₂. Sum uses XOR; Carry also needs AND and OR because AND alone misses Cᵢₙ.
Question 6, UGC NET 2015
Consider a full adder with the following input values
(1) x = 1, y = 0 and Cᵢ (carry input) = 0
(2) x = 0, y = 1 and Cᵢ = 1
Compute the values of S (sum) and Cₒ (carry output) for the above input values
A. S = 1, Cₒ = 0 and S = 0, Cₒ = 1
B. S = 0, Cₒ = 0 and S = 1, Cₒ = 1
C. S = 1, Cₒ = 1 and S = 0, Cₒ = 0
D. S = 0, Cₒ = 1 and S = 1, Cₒ = 0
Answer: A. Case (1), 1 + 0 + 0 = 1₂, gives (S, Cₒ) = (1, 0). Case (2), 0 + 1 + 1 = 10₂, gives (S, Cₒ) = (0, 1); this order matches A.
Half-subtractor and full-subtractor MCQs: Questions 7-9
Question 7, ISRO 2016
For a binary half-subtractor having two inputs A and B, the correct set of logical expressions for the outputs D (= A minus B) and X (=borrow) are
A. D = AB + A'B , X = A'B
B. D = A'B + AB' , X = AB'
C. D = A'B + AB' , X = A'B
D. D = AB + A'B , X = AB'
Answer: C. XOR gives D = A'B + AB', which is 1 when inputs differ. Borrow occurs only at A = 0, B = 1, so X = A'B.
Question 8, BEL 2023
Full-Subtractor has _____ inputs and _____ outputs.
A. 2; 2
B. 2; 3
C. 3; 2
D. 3; 3
Answer: C. Inputs are minuend A, subtrahend B, and borrow-in Bᵢₙ; outputs are Difference and borrow-out. A half subtractor omits Bᵢₙ but still has two outputs.
Question 9, DSSSB 2022
Which of the following statements is/are true about Half-Subtractor?
(i) D = x⊕y, where D is difference, and x, y are inputs.
(ii) B = xy, where B is borrow, and x, y are inputs.
A. Only (i)
B. Only (ii)
C. Both (i) and (ii)
D. Neither (i) nor (ii)
Answer: A. Statement (i) is the XOR difference rule. Statement (ii) gives Carry xy, but Borrow is x'y: at x = 0, y = 1, borrowing occurs although xy = 0.
Multi-bit adders and ripple-carry timing: Questions 10-11
Question 10, GATE 1999
The number of full adders and half adders required to add two 16-bit numbers is:
A. 8 half-adders, 8 full-adders
B. 1 half-adder, 15 full-adders
C. 16 half-adders, 0 full-adders
D. 4 half-adders, 12 full-adders
Answer: B. Bit 0 adds two least significant bits, so one half adder is enough. Bits 1 to 15 take a previous carry, requiring 15 full adders; 1 + 15 = 16 stages.
Question 11, ISRO 2020
In a 8-bit ripple carry adder using identical full adders, each full adder takes 34 ns for computing sum. If the time taken for 8-bit addition is 90 ns, find time taken by each full adder to find carry.
A. 6 ns
B. 7 ns
C. 10 ns
D. 8 ns
Answer: D. Carry crosses seven boundaries before final Sum, so 34 + 7tᴄ = 90. Thus 7tᴄ = 56 and tᴄ = 8 ns; 90 ÷ 8 wrongly ignores Sum delay.
Binary adder-subtractor mode control: Question 12
Question 12
A binary adder can be converted into a Binary adder/subtractor by using which of the following gates and inputs?
A. XOR, 1
B. AND, 1
C. XOR, 0
D. AND, 0
Answer: A. Each B bit is XORed with mode M, and the same M feeds the least significant carry-in. At M = 1, B ⊕ 1 = B', so the circuit computes A + B' + 1, the two's-complement form of A minus B. Take A = 0101₂ (5) and B = 0011₂ (3): B' = 1100₂, and 0101₂ + 1100₂ + 1 = 1 0010₂. Discard the final carry to read 0010₂, which is 2. Review this step in Number Systems and Base Conversions Explained.
Adders and subtractors MCQ patterns that exams repeat
KnowledgeGate's question bank carries over 40 adders and subtractors questions, and six moves repeat across them:
Identify a circuit, or the gates that build it, from its inputs and outputs (Questions 1, 2, 4, 5, 8).
Choose the Sum, Carry, Difference or Borrow expression (Questions 3, 7, 9).
Evaluate a full adder on a given input row (Question 6).
Count adders in an
n-bit chain (Question 10).Trace the critical carry delay (Question 11).
Convert an adder into an adder-subtractor with mode control (Question 12).
Four errors decide most of the lost marks:
A half adder has no carry-in.
xyis Carry, butx'yis Borrow.A full subtractor has three inputs and two outputs.
Ripple delay follows carry, not stage count multiplied by Sum delay.
Use Combinational Circuits: MUX, Decoders, Adders for the wider circuit picture. The GATE CS exam preparation category connects it to the remaining syllabus.
Adders and subtractors: the short version and next step
Retrieve this: half means two inputs; full adds carry-in or borrow-in; XOR gives Sum or Difference; AND and OR resolve Carry or Borrow; multi-bit questions add stages and delay.
Redraw all four circuits from memory, then reattempt Questions 5, 9, 11 and 12 without formulas. For structured Digital Electronics lessons and practice, continue with GATE Guidance by Sanchit Sir.
