CLA & Arithmetic Logic MCQs: 10 Solved Questions with Explanations

CLA questions combine four skills: recognising generate and propagate logic, reading asymptotic delay, counting gates or ROM lines, and calculating a critical path. The main difficulty is choosing the intended model before touching the options. Identify the architecture and constraints first, then compute only the terms or path that determine the answer.

1. Build the carry model once before solving

For bit i, use G_i = A_i B_i, P_i = A_i XOR B_i, C_(i+1) = G_i + P_i C_i, and S_i = P_i XOR C_i. Some texts use OR for propagate. Follow the definition supplied and do not mix conventions.

Take A = 1011, B = 0110, and C_0 = 0. From bit 0 to bit 3, (P_i, G_i) is (1,0), (0,1), (1,0), (1,0), while the carries are C_1=0, C_2=1, C_3=1, C_4=1. Thus S_3S_2S_1S_0 = 0001 and C_4S_3S_2S_1S_0 = 10001, or decimal 17. This checks 11 + 6.

A ripple adder waits for preceding carries. A CLA expands carry equations for parallel formation or a bounded-fan-in prefix tree. Review the building blocks in Combinational Circuits: Multiplexers, Decoders and Adders.

2. Recognition questions: what CLA changes

CLA reduces carry dependency by forming carry terms from generate and propagate signals. The speed gain costs extra hardware; it does not guarantee simpler logic, fewer gates, or lower power.

Question 1, Bihar STET 2025

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Which type of adder is designed to overcome the propagation delay issues in ripple carry adders and generate carry signals more efficiently?

1. Ripple Carry Adder

2. Carry Look-Ahead Adder

3. Binary Adder

4. Half Adder

Answer: Option 2, Carry Look-Ahead Adder.

In an RCA, stage i+1 must wait for carry C_(i+1) from stage i. A CLA instead derives carry terms from P_i and G_i, reducing that serial wait. A generic binary adder is not a distinct speed-up architecture, while a half adder cannot even accept a carry-in.

Question 2, Bihar STET 2025

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What is the key advantage of using a carry-lookahead adder instead of a ripple-carry adder?

1. Simplicity of design

2. Faster propagation delay

3. Lower power consumption

4. Reduced gate count

Answer: Option 2, Faster propagation delay.

A 4-bit RCA finds C_1, then C_2, C_3, and C_4; a CLA forms expanded carries in parallel. Extra hardware buys speed, so simplicity and reduced gate count are wrong. Lower power is not guaranteed. Try Digital Electronics Combinational Circuits MCQs next.

3. Growth-rate questions: linear paths, lookahead trees and fan-in

The answer changes with architecture and fan-in. Separate area from delay before naming the complexity.

Question 3, GATE 1999

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The maximum gate delay for any output to appear in an array multiplier for multiplying two n-bit numbers is:

1. O(n²)

2. O(n)

3. O(log n)

4. O(1)

Answer: Option 2, O(n).

An array multiplier has n² partial-product cells, which describes area. Its longest path crosses a linear number of adder or carry stages. For n=8, 64 bit-pair partial products exist, but delay follows the rows or diagonals, not all 64 cells.

Question 4, GATE 1997

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An N-bit carry look ahead adder, where N is a multiple of 4, employs ICs 74181 (4 bit ALU) and 74182 (4 bit carry look ahead generator).

The minimum addition time using the best architecture for this adder is

1. proportional to N

2. proportional to logN

3. a constant

4. none of the above

Answer: Option 2, proportional to logN.

For N=64, use 16 four-bit 74181 blocks. Four first-level 74182 generators combine four blocks each; one second-level 74182 combines those groups. Each level reduces unresolved groups fourfold, so the height is proportional to log_4 N, or O(log N).

Question 5, GATE 2016

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Consider a carry lookahead adder for adding two $n$-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is

1. $\Theta (1)$

2. $\Theta (\log(n))$

3. $\Theta (\sqrt{n})$

4. $\Theta (n)$

Answer: Option 2, Theta(log n).

Fan-in two prevents one gate combining every carry term. A generate-propagate prefix tree doubles its range at each level: 1, 2, 4, 8, and so on. Covering n bits needs log_2 n levels; the final sum XOR adds constant depth.

4. Delay numericals: count the path, not every gate

Write the worst-case sequential path as a sum. Do not multiply parallel operations by the bit count.

Question 6, GATE 2004

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A 4-bit carry lookahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic.

1. 4 time units

2. 6 time units

3. 10 time units

4. 12 time units

Answer: Option 2, 6 time units.

The path is 2 units for XOR-style propagate, 2 through the two-level AND-OR carry network, and 2 for the final sum XOR: 2 + 2 + 2 = 6 time units. Parallel P_i/G_i generation is not multiplied by four.

Question 7, Indian Space Research Organization 2017

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A 32 bit adder is formed by cascading 4 bit CLA adder. The gate delays (latency) for getting the sum bits is

1. 16

2. 18

3. 17

4. 19

Answer: Option 3, 17.

There are 32/4 = 8 CLA blocks. The carry crosses 7 boundaries at 2 gate delays each, then the selected block needs 3 delays for the sum. Thus 7 x 2 + 3 = 17 gate delays. Eight boundaries would overcount.

5. Hardware sizing: gate counts and ROM dimensions

Gate-count questions may supply intermediate signals. ROM questions separate address inputs from output bits.

Question 8, GATE 2007

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In a look-ahead carry generator, the carry generate function G_i and the carry propagate function P_i for inputs A_i and B_i are given by:

P_i = A_i ⨁ B_i and G_i = A_iB_i. The expressions for the sum bit S_i and the carry bit C_(i+1) of the look-ahead carry adder are given by:

S_i = P_i ⨁ C_i and C_(i+1) = G_i + P_iC_i, where C_0 is the input carry. Consider a two-level logic implementation of the look-ahead carry generator. Assume that all P_i and G_i are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to implement the look-ahead carry generator for a 4-bit adder with S_3, S_2, S_1, S_0 and C_4 as its outputs are respectively:

1. 6, 3

2. 10, 4

3. 6, 4

4. 10, 5

Answer: Option 2, 10, 4.

The expanded carries need 1, 2, 3, and 4 AND product terms respectively:

• C_1 = G_0 + P_0C_0

• C_2 = G_1 + P_1G_0 + P_1P_0C_0

• C_3 = G_2 + P_2G_1 + P_2P_1G_0 + P_2P_1P_0C_0

• C_4 = G_3 + P_3G_2 + P_3P_2G_1 + P_3P_2P_1G_0 + P_3P_2P_1P_0C_0

Thus 1+2+3+4=10 AND gates and 4 OR gates are required. Do not recount available P_i/G_i or sum XOR hardware.

Question 9, UGC NET 2014

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The size of the ROM required to build an 8-bit adder/subtractor with mode control, carry input, carry output and two’s complement overflow output is given as

1. 2^16 × 8

2. 2^18 × 10

3. 2^16 × 10

4. 2^18 × 8

Answer: Option 2, 2^18 × 10.

Address inputs are 8 bits each for A and B, 1 mode bit, and 1 carry-in, giving 18 lines and 2^18 rows. Each row stores 8 result bits, carry-out, and overflow, giving 10 bits. Continue with Digital Electronics MCQs.

6. Counting valid operand pairs

Bounded-pairs counting starts from each operand’s legal range, not from carry equations.

Question 10, UPPSC Polytechnic Lecturer 2018

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A and B are two unsigned 8-bit numbers such that A + B <= 2⁸. The number of possible combinations of A and B is:

1. 2⁹

2. 2⁸

3. 33,151

4. 2⁴ - 1

Answer: Option 3, 33,151.

Both operands range from 0 to 255. For A=0 and A=1, all 256 B values work. For A=2..255, valid B counts descend from 255 to 2. Ordered pairs total 256 + 256 + (255 + 254 + ... + 2) = 512 + 32,639 = 33,151.

7. Traps that cost marks in CLA questions

• Area is not delay. An array multiplier can have O(n²) cells but O(n) critical-path delay.

• Lookahead is not automatically constant time. Bounded fan-in produces logarithmic tree depth.

• Four-bit CLA blocks can still ripple. Cascading fast blocks does not create lookahead between them.

• Do not count supplied signals twice. If P_i and G_i are available, exclude their generation unless asked.

Check units: time units differ from nanoseconds; ROM size is rows × bits per row; ordered pairs differ from unordered pairs. Derive before reading the options. If they disagree, recheck the path or wording.

8. Answer key and next practice step

1-B, 2-B, 3-B, 4-B, 5-B, 6-B, 7-C, 8-B, 9-B, 10-C

For retrieval practice, write C_4 without notes, explain fan-in two's logarithmic depth, and size a ROM from its input and output lines.

If the architecture questions were difficult, use GATE Guidance by Sanchit Sir. For timed mixed practice, move to the GATE Test Series. The GATE preparation category is the broader route. Then make a second pass through the ten question links, solving each before opening its explanation.