Special Logic Circuits MCQs: 12 Solved Questions on Adders, Encoders, PLA and DAC

Special logic circuits questions look unrelated until you classify them. Most test present-input logic, parity or comparison, data routing and encoding, programmable logic, arithmetic hardware, or conversion. This set gives you exactly 12 published questions, arranged from quick recognition to multi-step hardware counts and Boolean identities.

Before reading each explanation, choose an option and write one line of reasoning. That small pause will reveal whether you recognised the circuit or merely recognised the answer. KnowledgeGate has over 40 published questions in this Special Logic Circuits subtopic, and the wider GATE CS Exam Preparation page can help you place it inside the full syllabus.

1. Special logic circuits: the compact toolkit before the MCQs

Use the circuit's inputs, outputs and job to identify it. The combinational-circuit design method starts from the same habit.

Calibrate that method with an 8-to-3 encoder. Let only D5 = 1, with D0, D1, D2, D3, D4, D6, D7 = 0. Then A2 = D4 + D5 + D6 + D7 = 1, A1 = D2 + D3 + D6 + D7 = 0, and A0 = D1 + D3 + D5 + D7 = 1. Therefore, A2A1A0 = 101₂ = 5.

2. Special Logic Circuits MCQs 1-3: combinational behaviour, XOR and parity

Question 1

(CDAC CCAT 2017)

If the output of a circuit depends entirely on the inputs at that time, it is called a:

• (a) Sequential Logic Circuit

• (b) Asynchronous Circuit

• (c) Synchronous Circuit

• (d) Combinational Logic Circuit

Answer: (d) Combinational Logic Circuit.

A combinational output uses current inputs and no state. A sequential circuit also uses previous state. Synchronous and asynchronous describe timing, not memory.

Question 2

(DSSSB 2021)

A 2-way switch works as follows:

Both switches ON → Light OFF

Both switches OFF → Light OFF

One switch ON and the other OFF → Light ON

Which logic gate can be used to implement this?

• (a) OR

• (b) AND

• (c) NAND

• (d) XOR

Answer: (d) XOR.

The rows 00 -> 0, 01 -> 1, 10 -> 1, 11 -> 0 match XOR: the light is on only for unequal states. OR fails at 11.

Question 3

(TPSC 2026 solved parity question)

What is the expression for even parity for 3 bits a, b, c ?

• (a) a ⊕ b ⊕ c

• (b) (a ⊕ b ⊕ c)'

• (c) a ∧ b ∧ c

• (d) a ∨ b ∨ c

Answer: (a) a ⊕ b ⊕ c.

Let this be parity bit p. For a,b,c = 1,0,0, XOR gives p = 1, making two 1s. For 1,0,1, p = 0, preserving two 1s. The complement gives opposite parity.

3. Special Logic Circuits MCQs 4-6: adders and threshold logic

Question 4

(UGC NET 2016)

Match the following :

$\begin{array}{clcl} & \textbf{List-I} && \textbf{List-II} \\ \text{a.} & \text{Controlled inverter} & \text{i.} & \text{a circuit that can add 3 bits} \\ \text{b.} & \text{Full adder} & \text{ii.} & \text{a circuit that can add two binary numbers} \\ \text{c.} & \text{Half adder} & \text{iii.} & \text{a circuit that transmits a binary word or} \\ &&& \text{its 1’s complement} \\ \text{d.} & \text{Binary adder} & \text{iv.} & \text{a logic circuit that adds 2 bits} \\ \end{array}$

Codes :

• (a) a-iii, b-ii, c-iv, d-i

• (b) a-ii, b-iv, c-i, d-ii

• (c) a-iii, b-iv, c-i, d-ii

• (d) a-iii, b-i, c-iv, d-ii

Answer: (d) a-iii, b-i, c-iv, d-ii.

A controlled inverter passes a word or its 1's complement. A full adder accepts two bits plus carry-in, a half adder accepts two bits, and a binary adder combines multi-bit numbers. Thus, a-iii, b-i, c-iv, d-ii.

Question 5

(UGC NET 2014)

The BCD adder to add two decimal digits needs minimum of

• (a) 6 full adders and 2 half adders

• (b) 5 full adders and 3 half adders

• (c) 4 full adders and 3 half adders

• (d) 5 full adders and 2 half adders

Answer: (d) 5 full adders and 2 half adders.

The first addition uses four full adders. For correction 0110₂, bit 1 needs a half adder, bit 2 a full adder with carry, and bit 3 a half adder. Total: 4 + 1 = 5 full adders and 2 half adders.

Question 6

(GATE 2004)

A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 by 0001, ..., 9 by 1001. A combinational circuit is to be designed which takes these 4 bits as input and outputs 1 if the digit ≥ 5, and 0 otherwise. If only AND, OR and NOT gates may be used, what is the minimum number of gates required?

• (a) 2

• (b) 3

• (c) 4

• (d) 5

Answer: (b) 3.

Let A B C D be the bits, with A as the 8's bit. Valid codes simplify to A + B(C + D): one OR, one AND and one final OR. Total: three gates.

4. Special Logic Circuits MCQs 7-9: encoders, PLA and majority logic

Question 7

(UGC NET 2022 encoder question)

Consider a logic gate circuit, with 8 input lines $\left(\mathrm{D}_{0}, \mathrm{D}_{1} \ldots \ldots \mathrm{D}_{7}\right)$ and 3 output lines $\left(\mathrm{A}_{0}, \mathrm{~A}_{1}, \mathrm{~A}_{2}\right)$ specified by following operations

$\begin{array}{l} A_{2}=D_{4}+D_{5}+D_{6}+D_{7} \\ A_{1}=D_{2}+D_{3}+D_{6}+D_{7} \\ A_{0}=D_{1}+D_{3}+D_{5}+D_{7} \end{array}$

Where + indicates logical OR operation. This circuit is

• (a) 3×8 multiplexer

• (b) Decimal to BCD converter

• (c) Octal to Binary encoder

• (d) Priority encoder

Answer: (c) Octal to Binary encoder.

Each equation selects indices whose binary bit is 1. With only D5 = 1, A2A1A0 = 101, index 5. Eight one-hot inputs and three outputs identify an octal-to-binary encoder, without priority logic.

Question 8

(ISRO 2013 PLA fuse-count question)

How many programmable cross-point fuses are required in a PLA with 16 inputs, 8 outputs, 8 OR gates, and 32 AND gates?

• (a) 1032

• (b) 776

• (c) 1280

• (d) 1536

Answer: (c) 1280.

The AND plane count is 32 x (16 + 16) = 1024. The OR plane count is 32 x 8 = 256. Total: 1024 + 256 = 1280.

Question 9

(GATE 2025, MSQ)

Let $𝑋$ be a 3-variable Boolean function that produces output as ‘1’ when at least two of the input variables are ‘1’. Which of the following statement(s) is/are CORRECT, where $𝑎, 𝑏, 𝑐, 𝑑,𝑒$ are Boolean variables?

• (a) $𝑋(𝑎, 𝑏, 𝑋(𝑐, 𝑑,𝑒)) = 𝑋(𝑋(𝑎, 𝑏, 𝑐), 𝑑,𝑒)$

• (b) $𝑋(𝑎, 𝑏, 𝑋(𝑎, 𝑏, 𝑐)) = 𝑋(𝑎, 𝑏, 𝑐)$

• (c) $𝑋(𝑎, 𝑏, 𝑋(𝑎, 𝑐, 𝑑)) = (𝑋(𝑎, 𝑏, 𝑎) AND 𝑋(𝑐, 𝑑, 𝑐))$

• (d) $𝑋(𝑎, 𝑏, 𝑐) = 𝑋(𝑎, 𝑋(𝑎, 𝑏, 𝑐), 𝑋(𝑎, 𝑐, 𝑐))$

Answer: (b) and (d).

For (b), matching a,b determine both sides; otherwise both equal c. For (d), X(a,c,c) = c; if a = c, it controls both sides, otherwise both equal b.

Reject (a) with a=b=0, c=d=e=1: left 0, right 1. Reject (c) with a=1,b=0,c=0,d=1: left 1, right 0.

5. Special Logic Circuits MCQs 10-12: multipliers, ROM sizing and DAC scaling

Question 10

(GATE 2003)

Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is

• (a) Θ(1)

• (b) Θ(log n)

• (c) Θ(n)

• (d) Θ(n2)

Answer: (c) Θ(n).

Partial products form in constant depth, but the critical path crosses Θ(n) adder and carry stages. Unit delay per stage therefore gives Θ(n) total delay. An array is not a logarithmic-depth tree.

Question 11

(GATE 2012 ROM multiplier question, also asked in TPSC 2025)

The amount of ROM needed to implement a 4-bit multiplier is:

• (a) 64 bits

• (b) 128 bits

• (c) 1 Kbits

• (d) 2 Kbits

Answer: (d) 2 Kbits.

Two 4-bit operands give 4 + 4 = 8 address inputs and 2^8 = 256 words. The maximum product, 15 x 15 = 225 = 11100001₂, needs 8 bits. Capacity: 256 x 8 = 2048 bits = 2 Kbits.

Question 12

(CDAC CCAT 2017)

A 6 bit DAC has a current output. For a digital input of 110010, the output current of 15mA is produced. What is the Output Current when the digital input is 111001?

• (a) 20mA

• (b) 17.1mA

• (c) 188.1mA

• (d) 13.3mA

Answer: (b) 17.1mA.

Convert the codes: 110010₂ = 50, 111001₂ = 57. Linear scaling gives I₂ / 15 = 57 / 50, hence I₂ = 15 x 57 / 50 = 17.1 mA.

6. How exams test special logic circuits

Exams use three recurring demands:

• Recognise a block from its rule: Questions 1 to 4 and 7.

• Count or minimise hardware: Questions 5, 6, 8, 10 and 11.

• Compute a value or test an identity: Questions 3, 9 and 12.

For recognition, write a truth table. For hardware, mark inputs, output width and critical path. Convert binary to decimal before a DAC ratio. Test a Boolean identity with one decisive counterexample before proving it.

Continue with Combinational Circuits MCQs: 12 Solved GATE Questions for mixed practice. If routing and logic simplification blur together, work through Multiplexer Realization for GATE.

7. Special logic circuits: the short version and next step

Keep this six-line memory card:

• XOR means unequal inputs.

• Parity is repeated XOR.

• A full adder includes carry-in.

• An encoder outputs the active input's binary index.

• A PLA fuse count covers both programmable planes.

• ROM capacity equals number of words times output width.

Reattempt Questions 5, 8, 9 and 11 without the answers. They test application, not recognition.

For a structured route through Digital Electronics and GATE CS, GATE Guidance by Sanchit Sir provides the broader sequence. Topic-only readers can continue with the free combinational-circuit material above.