Sync Counter Design MCQs: 11 Solved Questions on Modulus, State Sequences and Excitation Logic

Synchronous-counter problems become easier once four operations are separated: count internal states, distinguish repeated output phases, trace simultaneous flip-flop updates and derive excitation inputs. Write the present and next states in binary before choosing a formula. A repeated visible count may still need extra phase bits, and common-clock flip-flops always sample the old state together.

Sync counter design rules to keep beside the questions

An n-flip-flop register stores at most 2^n states. A mod-N counter needs the smallest n satisfying 2^n >= N. Boundaries are 2^4=16, 2^8=256 and 2^9=512.

Visible output and internal phase differ when one value has different successors in a cycle. Internal states must then remember each occurrence. Thus, eight clocks may require three flip-flops even if they display only 0,1,2,3.

Remember D=Q(next). A JK flip-flop toggles for J=K=1 and holds for J=K=0. In a binary down counter, a higher bit toggles when every lower present bit is 0.

All flip-flops sample old values at the active edge, then change after propagation delay. Sequential Circuits MCQs: 11 Solved Questions on Flip-Flops and Counters owns the broad mix of latches, ring and Johnson counters, and state analysis. Its mod-258 and D-to-JK questions are reused here to anchor the storage boundary and common-clock trace before this set moves into repeated phases, excitation equations, enables and composite states.

Mod-N counter design MCQs: Questions 1-3

Question 1: minimum storage for a mod-16 counter

Minimum number of flip-flops required to construct a mod 16 counter

Answer: 4. Three flip-flops provide 2^3=8<16 states, while four provide 2^4=16 states. Four are therefore sufficient and minimal; 16 is the number of counter states, not the number of storage bits.

Question 2: the power-of-two boundary at mod-258

GATE 2011. Open the live solved question.

The minimum number of D flip-flops needed to design a mod-258 counter is

• (a) 9

• (b) 8

• (c) 512

• (d) 258

Answer: (a) 9. Eight D flip-flops provide 2^8=256 states, which is two fewer than 258, whereas nine provide 2^9=512. The counter uses 258 valid states, leaving 512-258=254 unused encodings that a complete design must handle safely.

Question 3: the same boundary at modulo-272

UGC NET 2015, June. Open the live solved question.

The number of flip-flops required to design a modulo-272 counter is

• (a) 8

• (b) 9

• (c) 27

• (d) 11

Answer: (b) 9. With the given modulus N=272, the boundary is 2^8=256<272<=512=2^9. Eleven flip-flops could encode enough states but would not be minimal, while 27 is not a storage-width calculation.

Repeated-output synchronous counters: Questions 4-5

Question 4: each count value held for two clocks

GATE 2015 Set 2. Open the live solved question.

The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0,0,1,1,2,2,3,3,0,0,…) is __________ .

Answer: 3. The cycle has eight distinguishable clock phases: first 0, second 0, first 1, second 1, first 2, second 2, first 3 and second 3. Two bits can display the four values, but a third phase bit distinguishes hold from advance, and 2^3=8 exactly covers all phases.

Question 5: each count value held for four clocks

A synchronous counter using JK flip-flops follows 0 → 0 → 0 → 0 → 1 → 1 → 1 → 1 → 2 → 2 → 2 → 2 → 3 → 3 → 3 → 3 → 0, and so on.

What is the minimum number of flip-flops required to implement this counter?

Answer ________ .

Answer: 4. There are 4 values × 4 clock phases per value = 16 distinguishable internal states. Three flip-flops encode only eight states, while four encode exactly 2^4=16; the display alone cannot identify the first, second, third or fourth occurrence of a value.

Clock movement and simultaneous sampling: Questions 6-7

Question 6: wrap a 7-bit up counter from 84 to 20

The number of clock pulses needed to change the contents of a 7-bit up counter from 1010100 to 0010100 is _______?

Answer: 64. The endpoints are 1010100₂=84 and 0010100₂=20; a 7-bit counter is modulo 128, so the forward distance is (20-84) mod 128=64. Equivalently, use 43 pulses from 84 to 127, one pulse from 127 to 0, and 20 pulses from 0 to 20, giving 43+1+20=64.

Question 7: trace a D flip-flop driving a JK flip-flop

GATE 2015 Set 1. Open the live solved question.

A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.

• (a) 0110110…

• (b) 0100100…

• (c) 011101110…

• (d) 011001100…

Answer: (a) 0110110…. Starting at (Q_D,Q_JK)=(1,0), successive rising edges produce (0,1),(1,1),(1,0),(0,1),(1,1),(1,0). Reading Q_JK, including its initial value, gives 0,1,1,0,1,1,0; non-zero propagation delay ensures both devices sample the old pair, not one another's newly changed outputs.

D and JK excitation logic: Questions 8-9

Question 8: derive D0 for the sequence 0, 2, 1, 3

A 2-bit synchronous counter built with D flip-flops follows the sequence 0, 2, 1, 3, 0, and so on. The partial circuit below leaves input D₀ unknown.

Determine X, the input D₀.

• (a) Q₁

• (b) Q₀

• (c) Q₁ ⊕ Q₀

• (d) Q₁ ⊙ Q₀

Answer: (c) Q₁ ⊕ Q₀. The binary transitions are 00->10->01->11->00. Because D₀=Q₀(next), the input values for present states 00,10,01,11 are 0,1,1,0, exactly the XOR truth table; in sum-of-products form, D₀=Q₁Q₀' + Q₁'Q₀.

Question 9: minimise JK inputs for a 3-bit down counter

UGC NET 2017, January. Open the live solved question.

A binary 3-bit down counter uses J-K flip-flops FFᵢ with inputs Jᵢ, Kᵢ and outputs Qᵢ for i = 0, 1, 2. Which of the following minimized input expressions are correct?

I. J₀ = K₀ = 0

II. J₀ = K₀ = 1

III. J₁ = K₁ = Q₀

IV. J₁ = K₁ = Q₀′

V. J₂ = K₂ = Q₁Q₀

VI. J₂ = K₂ = Q₁′Q₀′

• (a) I, III, V

• (b) I, IV, VI

• (c) II, III, V

• (d) II, IV, VI

Answer: (d) II, IV, VI. Q₀ toggles every clock, so J₀=K₀=1; Q₁ toggles when present Q₀=0, so J₁=K₁=Q₀'; and Q₂ toggles when Q₁Q₀=00, so J₂=K₂=Q₁'Q₀'. Transitions 100->011 and 000->111 both confirm that the most-significant bit toggles only when both lower present bits are zero.

If deriving inputs feels manageable but tracing a completed circuit costs time, work through the Sync Counter Analysis MCQs next.

Enable inputs and composite state spaces: Questions 10-11

Question 10: hold or count under external input x

DSSSB 2022. Open the live solved question.

A clocked sequential circuit is to be designed (using D flip-flops) that goes through sequence of repeated binary states 00, 01, 10, and 11 when value of external input x = 1. The state of the circuit remains unchanged when x = 0. Which statement is correct about the design of this circuit?

• (a) It requires 3 flip-flops.

• (b) It has one external output.

• (c) The input of the left-most flip flop (corresponding to most significant bit of the state) does not depend on external input x.

• (d) The input of the right-most flip flop (corresponding to least significant bit of the state) depends on external input x.

Answer: (d). Two state bits represent 00,01,10,11. The least-significant bit holds for x=0 and toggles for x=1, giving D₀=Q₀ XOR x; the most-significant input also uses the enable, for example D₁=Q₁ XOR (xQ₀), so C is false as well.

Question 11: count nine unique ordered-pair states

A synchronous counter is to be designed using JK flip-flops to follow the sequence of decimal states:

(0,0),(1,0),(1,1),(2,1),(3,1),(3,2),(2,2),(2,0),(0,1),(0,0),…

Each listed state occurs once before the cycle returns to (0,0). At state (2,2), the counter transitions conditionally based on external input X:

If X = 1, the next state is (2,0).

If X = 0, the next state is (0,1).

States are encoded in binary using the minimum number of JK flip-flops required to represent all unique states.

Question:

What is the minimum number of JK flip-flops required to implement this synchronous counter?

Answer _______

Answer: 4. The nine distinct pairs are (0,0),(1,0),(1,1),(2,1),(3,1),(3,2),(2,2),(2,0),(0,1). Three flip-flops encode only 2^3=8 states, while four encode 16; the branch adds no state because both possible destinations already belong to the nine-state set.

Sync counter design score map and next practice step

Use each miss to choose one repair. For Questions 1-3, practise ceil(log2 N) around powers of two. For Questions 4-5, count clock phases rather than displayed values. For Questions 6-7, retrace modulo distance and simultaneous old-state sampling. For Questions 8-10, rebuild D next-state values and JK toggle conditions. For Question 11, count unique composite states before selecting register width. Browse the GATE CS Exam Preparation Courses & Test Series for the wider route. Use GATE Guidance by Sanchit Sir when state tables and excitation equations need structured rebuilding; move to the GATE Test Series once you can solve Questions 6, 8 and 9 without the worked steps.