Sequential Logic and Latches MCQs: 10 Solved Questions with Explanations

Sequential-logic questions mix three different jobs: recognising memory, reading a state transition, and applying active-HIGH versus active-LOW latch rules. A learner who remembers only a truth table can still reverse set and reset or miss what a forbidden input does. These 10 questions test a different decision each: identify memory, apply flip-flop or latch rules, trace the next state, and count multivibrator states. Attempt each question before reading its explanation, and write present state -> next state beside every latch or state-machine item; if latch, flip-flop and state machine still feel interchangeable, repair that foundation first with Sequential Circuits: Flip-Flops and Counters.

Sequential logic and latch rules to use before solving

A combinational circuit has no stored state, so its current output can be written as Y_n = f(X_n). A sequential circuit carries state: Q_(n+1) = f(Q_n, X_n). Its output is Y_n = g(Q_n) in a Moore model or Y_n = g(Q_n, X_n) in a Mealy model. The stored Q_n is how relevant past inputs continue to matter.

Now trace a cold start. With Q_n=0, a T flip-flop at T=1 gives Q_(n+1)=1. A second active edge with T=1 complements it back to 0. At the next edge, T=0 holds that state at 0. The complete trace is 0 -> 1 -> 0 -> 0.

Sequential circuit memory and T flip-flop MCQs

Question 1: Identify what a sequential output depends on

UGC NET 2014

The output of a sequential circuit depends on

• A. present input only

• B. past input only

• C. both present and past input

• D. past output only

Answer: C. both present and past input. The present state summarises the relevant past, while the current input can affect the next state and, in a Mealy circuit, the current output. A memory element carries that state from one evaluation step to the next. This is the best category-level distinction among the choices, not a claim that every Moore output directly uses the present input. A combinational circuit is different because it has no stored state.

Question 2: Apply the T flip-flop toggle rule

CDAC CCAT 2025

A T flip-flop toggles its output when T equals:

• A. 0

• B. 1

• C. Both 0 and 1

• D. Neither

Answer: B. 1. The characteristic relation is Q_(n+1) = T XOR Q_n. For Q_n=0, setting T to 1 gives 1 XOR 0 = 1; for Q_n=1, it gives 1 XOR 1 = 0. At T=0, the relation becomes Q_(n+1)=Q_n, so the state holds. At T=1, the state toggles on each active edge; at T=0, it holds.

JK output states and the NOR SR forbidden input

Question 3: Count the possible output states of one JK flip-flop

CDAC CCAT 2025

A JK flip-flop has how many possible output states?

• A. 1

• B. 2

• C. 3

• D. 4

Answer: B. 2. J and K allow four input combinations, but a single flip-flop stores only one bit. That stored output can be Q=0 or Q=1, so there are two output states regardless of which input pair produced them. The trap is counting four excitation cases as four stored states.

Question 4: Find the invalid input of a NOR SR latch

CDAC CCAT 2025

The invalid (race) input combination of an SR flip-flop using NOR gates is:

• A. S = 0, R = 0

• B. S = 0, R = 1

• C. S = 1, R = 0

• D. S = 1, R = 1

Answer: D. S = 1, R = 1. A 1 at either NOR-gate input forces that gate's output to 0, so this pair forces both latch outputs low and breaks the complementary-output condition. Releasing two forced-low outputs can also make the resulting stored state uncertain. In contrast, S=R=0 is the hold input for this active-HIGH latch. For an active-LOW NAND latch, the forbidden pair is reversed to S_bar=R_bar=0.

Cross-coupled latches and an XY excitation table

Question 5: Recognise a cross-coupled NAND latch

UGC NET 2011

A latch is constructed using two cross-coupled

• A. AND and OR gates

• B. AND gates

• C. NAND and NOR gates

• D. NAND gates

Answer: D. NAND gates. Feeding each NAND output back into the opposite gate forms an active-LOW SR latch with memory between evaluations. Option C is not the intended construction because the pair uses two gates of the same type, not one NAND and one NOR. Two cross-coupled NOR gates form a separate valid SR-latch implementation, but that does not change this option set.

Question 6: Find when an XY latch complements

Consider the following excitation table of XY latch.

The latch complements its state when ____.

• A. X=0, Y=1

• B. X=1, Y=0

• C. X=0, Y=0

• D. X=1, Y=1

Answer: A. X=0, Y=1. Complementing must work in both directions. The 0 -> 1 row requires X=0 and allows either Y, while the 1 -> 0 row requires Y=1 and allows either X. The common assignment is therefore X=0, Y=1.

State transitions and release from a forbidden NAND input

Question 7: Follow one state transition from A

TPSC 2024

In a sequential circuit with states A, B, and C, if the current state is A and the next state is determined by the input as follows:

- If input is 0, stay in A.

- If input is 1, transition to B.

What will be the next state if the current state is A and the input is 1?

• A. A

• B. B

• C. C

• D. Undefined

Answer: B. B. Write the two stated rules as delta(A,0)=A and delta(A,1)=B. Substituting the given present state A and input 1 selects delta(A,1)=B. State C is irrelevant because neither listed transition reaches it from A.

Question 8: Trace a cross-coupled NAND latch after 00, 11

Consider an SR flip-flop realized with two cross-coupled NAND gates. If the input sequence is 00, 11, then the output sequence will be ___.

• A. 11, 00, 11, 00

• B. 00, 11, 00, 11

• C. 11, 00, 10, 01

• D. 00, 11, 11, 00

Answer: A. 11, 00, 11, 00. In the ideal equal-delay model used by the item, active-LOW input 00 forces both outputs to 11. Changing the inputs to 11 releases that illegal symmetric state, so both NANDs compute 0 and then both compute 1 from the new feedback, producing 11 -> 00 -> 11 -> 00. Real gate delays are unequal, so a physical latch resolves unpredictably to one stable state instead of sustaining this symmetric alternation; that is why input 00 must be avoided.

For flip-flop and counter questions beyond this latch- and multivibrator-focused set, Sequential Circuits MCQs: 11 Solved Questions on Flip-Flops and Counters provides the broader mixed practice.

Monostable, astable and bistable state-count MCQs

Question 9: Count the states of a monostable multivibrator

DSSSB 2021

A monostable multivibrator has which of the following state(s)?

I. One stable state

II. One quasi-stable state

• A. Only I

• B. Only II

• C. Both I and II

• D. Neither I nor II

Answer: C. Both I and II. A monostable can rest indefinitely in its one stable state. A trigger moves it to one quasi-stable state for a limited interval, after which it returns. Both statements therefore identify its two state categories correctly.

Question 10: Correct the astable and bistable pairings

DSSSB 2021

Which of the following pair is/are correct?

I. Astable multivibrator – Flip Flop

II. Bistable multivibrator – Free running

• A. Only I

• B. Only II

• C. Both I and II

• D. Neither I nor II

Answer: D. Neither I nor II. The labels are crossed: an astable multivibrator is free-running because it has no stable state, while a bistable multivibrator is the flip-flop form because it has two stable states. Both statements are therefore incorrect. Keep the three-way memory aid exact: monostable = 1 stable, astable = 0 stable, bistable = 2 stable.

For questions that derive one flip-flop's inputs from another device's behaviour, Flip-Flops and Conversion MCQs: 12 Solved Questions practises the conversion method. The questions here instead test latch polarity, state transitions, and multivibrator states.

Sequential logic MCQ traps, answer check and next step

Answers: C, B, B, D, D, A, B, A, C, D.

Use the tally to choose your next revision step. 9-10 correct: move to mixed flip-flop and counter practice; 6-8: redo polarity and state tables; 0-5: rebuild the rule table above, trace Q_n -> Q_(n+1), then retry.

Short version

Locate memory, mark polarity, then test both states. Repair concepts with GATE Guidance by Sanchit Sir; wider route: GATE CS Exam Preparation.