Consider a combination of T and D flip-flops connected as shown below. The…

GATE · 2017 · CS · Set 1 · Computer Science & IT

Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop.

Initially, both Q0 and Q1 are set to 1 (before the 1st clock cycle). The outputs

  1. A.

    Q1Q0 after the 3rd cycle are 11 and after the 4th cycle are 00 respectively.

  2. B.

    Q1Q0 after the 3rd cycle are 11 and after the 4th cycle are 01 respectively.

  3. C.

    Q1Q0 after the 3rd cycle are 00 and after the 4th cycle are 11 respectively.

  4. D.

    Q1Q0 after the 3rd cycle are 01 and after the 4th cycle are 01 respectively.

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