Consider a three word machine instruction ADD A[R0], @ B The first operand…
2005
Consider a three word machine instruction
ADD A[R0], @ B The first operand (destination) "A [R0]" uses indexed addressing mode with R0 as the index register. The second operand (source) "@ B" uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand). The number of memory cycles needed during the execution cycle of the instruction is
- A.
3
- B.
4
- C.
5
- D.
6
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Correct answer: B
Answer: 4 memory cycles.
Explanation: Count only the memory accesses performed during the execution phase (do not include fetching the three instruction words).
Read the operand at A[R0] (indexed addressing): 1 memory read.
For the indirect source @ B: read memory at address B to obtain the effective address: 1 memory read.
Read the operand from the effective address obtained via B: 1 memory read.
Write the computed sum to the destination memory location (effective address of A[R0]): 1 memory write.
Total memory cycles during execution = 1 + 1 + 1 + 1 = 4.