Memory Management in Operating Systems: Paging, Virtual Memory and Worked Examples

Memory management feels like unrelated terms until one address must pass through a page number, page table, frame and offset, or one reference string must be traced without losing the replacement order. Allocation and fragmentation connect to paging, segmentation, the TLB, demand paging and replacement. A reliable method is to write the address split, preserve the offset, trace every frame after each reference, and convert access times to one unit before averaging.

Memory management in an OS: what the hardware and kernel solve

Memory management provides relocation for flexible placement, protection between processes, and controlled sharing of selected code/data across address spaces.

The CPU generates a logical address, RAM uses a physical address, and the memory management unit (MMU) translates. Compile-time binding fixes addresses; load-time adjusts at loading; execution-time enables dynamic relocation.

Contiguous allocation uses one region; paging maps equal pages to frames; segmentation preserves units; virtual memory keeps needed pages resident; replacement selects a victim. For a focused comparison, Memory management in OS: paging and segmentation explained distinguishes the two schemes; fit choices, TLB time and replacement traces complete the broader problem-solving map.

Contiguous allocation: first fit, best fit, worst fit and fragmentation

Fixed partitions cause internal fragmentation: 212 KiB in 256 KiB leaves 256 - 212 = 44 KiB. Variable partitions cause external fragmentation, where total free space suffices but no hole does.

For holes [100, 500, 200, 300, 600] KiB in address order and process P = 212 KiB:

These are alternatives, not simultaneous allocations. Best fit guarantees neither zero waste nor better future use. Compaction joins holes but requires relocation. Paging removes external fragmentation but adds table overhead and possible last-page waste.

Paging and page tables: complete address translation

System: 16-bit logical addresses, 1 KiB = 2^10 bytes pages, 32 KiB physical memory. The logical split is a 6-bit page and 10-bit offset. Its 32 frames (0 to 31) need a 5-bit frame and the same offset.

Page-table frame mappings: 0 -> 3, 1 -> 14, 2 -> present 0, 3 -> 27, 4 -> 6, 5 -> 9.

For logical address 5196 decimal (0x144C):

1. 5196 = 5 x 1024 + 76: page 5, offset 76.

2. Page 5 -> frame 9.

3. Physical address = 9 x 1024 + 76 = 9292 decimal (0x244C).

The offset is unchanged. 2250 = 2 x 1024 + 202 reaches valid page 2 with present = 0, causing a page fault, not frame 2 translation. The OS loads it, updates the table and retries. An illegal page traps.

There are 2^16 / 2^10 = 64 pages. With specified 4-byte entries, the table is 64 x 4 = 256 bytes. A PTE also stores status and protection, not only five frame bits.

Segmentation versus paging: logical units and limit checks

A segmented address is (segment, offset). Its entry holds base and limit. When 0 <= offset < limit, physical address = base + offset.

Segments (base, limit) are 0: (4000, 1000), 1: (9000, 600), 2: (12000, 1500). (2, 1220) is valid: 12000 + 1220 = 13220. (1, 650) traps because 650 >= 600, not 9650. Equality with the limit is invalid.

Segmented paging gives each segment its own page table.

Virtual memory, demand paging and the TLB: access-time arithmetic

Demand paging keeps a page on secondary storage until referenced. On fault, the OS validates, finds a frame or victim, writes a dirty victim if needed, reads, updates table and TLB state, then restarts.

With serial TLB lookup 10 ns, memory access 100 ns and hit ratio 0.90, a hit costs 10 + 100 = 110 ns; a non-faulting miss costs 10 + 100 + 100 = 210 ns:

EAT = 0.90 x 110 + 0.10 x 210 = 99 + 21 = 120 ns.

Parallel lookup differs. Memory Hierarchy and Virtual Memory: Paging, the TLB, and Address Translation covers the hardware connection.

Separately, ordinary access is 100 ns, fault service 8 ms = 8,000,000 ns, and fault probability 10^-6:

EAT = (1 - 10^-6) x 100 + 10^-6 x 8,000,000 = 99.9999 + 8 = 107.9999 ns, approximately 108 ns.

This is separate from the TLB assumptions.

Page replacement and thrashing: trace frames, not intuition

FIFO removes the oldest loaded page; LRU the least recently used; Optimal the one needed farthest ahead. Optimal is a benchmark because an OS cannot know the future stream.

Trace 7,0,1,2,0,3,0,4,2,3,0,3,2 through three empty frames. Each comma position aligns with that reference; ∅ means empty.

Totals: FIFO 10, LRU 9, Optimal 7 faults. All fault four times in the first four references. At 4, Optimal replaces 0, used later than 2 or 3. Final 3,2 hit for all.

A dirty victim needs write-back; reference bits enable Clock-like recency estimates. Thrashing means faults overtake useful work because working sets do not fit. Reduce multiprogramming pressure or allocate frames; changing policy alone is not a cure.

Memory-management questions: patterns and traps

Practise address splits, page/frame counts, table sizes, translations, TLB time, fit choices and replacement.

For focused practice, continue with Page Replacement Algorithms MCQs: FIFO, LRU, Optimal, or use GATE CS Exam Preparation for wider study.

Memory management in Operating Systems: the short version and next step

Recall: allocation chooses a hole; paging maps page to frame, preserving the offset; segmentation checks a limit; a TLB caches translations; demand paging may fault; replacement chooses a victim.

Paper check: 5196 gives page 5, offset 76, frame 9, physical 9292; (2, 1220) is valid at 13220; replacement totals are 10, 9, 7. If one fails, revisit its trace before timed work.

The GATE Test Series is an optional timed step. For only this topic, use the linked page-replacement MCQs.