Memory is where Computer Organisation and Operating Systems overlap, and GATE tests the seam relentlessly. Aspirants who see the memory hierarchy as one connected system, from a register to a disk block, answer address-translation and access-time numericals cleanly. Those who memorise paging in isolation stall on exactly those questions. Let us build the hierarchy, add virtual memory on top, and work a full virtual-to-physical translation.
The memory hierarchy: registers to disk
Computer memory is arranged as a hierarchy, trading speed for capacity and cost at each level. From fastest and smallest to slowest and largest:
Registers, inside the CPU, accessed in a single cycle.
Cache (L1, L2, L3), small and fast SRAM close to the CPU.
Main memory (RAM), larger DRAM, slower than cache.
Secondary storage (SSD or disk), huge, non-volatile, and orders of magnitude slower.
The guiding rule: keep the data you are about to use as high up the hierarchy as possible. Every level acts as a cache for the level below it.
[DIAGRAM: A pyramid of the memory hierarchy, registers at the narrow top through cache, main memory and disk at the wide base, with a "faster, smaller, costlier per byte" arrow up one side and "slower, larger, cheaper per byte" down the other.]
Locality of reference: why the hierarchy works
The hierarchy pays off because real programs exhibit locality of reference.
Temporal locality: a location accessed now is likely to be accessed again soon (a loop counter).
Spatial locality: locations near a recent access are likely next (walking through an array).
Caches exploit both by fetching a whole block and keeping recently used blocks. Without locality, the hierarchy would be no faster than its slowest level.
Virtual memory and paging
Virtual memory gives each process its own large, contiguous address space, independent of how much physical RAM exists or where its data actually sits. The mechanism is paging: the virtual address space is split into fixed-size pages, physical memory into equal-size frames, and the operating system maps any page to any frame. A page not currently in RAM lives on disk and is brought in on demand, causing a page fault that the OS services by loading the page into a free frame.
Because pages and frames are the same size, a virtual address splits cleanly into two parts: a high-order page number and a low-order offset within the page. The offset never changes during translation; only the page number is looked up.
Page tables and the TLB
The page table holds the frame number for each virtual page of a process. Translation reads the page number, indexes the page table to get the frame number, and combines it with the offset. The problem is that the page table lives in main memory, so every memory reference would cost two accesses: one for the page table, one for the data.
The fix is the Translation Lookaside Buffer (TLB), a small, fast, fully-associative cache of recent page-to-frame mappings. On a TLB hit the frame number is available immediately. On a TLB miss the hardware walks the page table in memory, then loads the mapping into the TLB for next time. The TLB works because page references have strong locality.
Address translation: a worked example
Take a 32-bit virtual address with a page size of 4 KB. Since 4 KB = 2¹², the offset is the low 12 bits and the page number is the high 20 bits.
Translate the virtual address 0x00003F7C:
Offset = the low 12 bits = 0xF7C.
Virtual page number = 0x00003F7C shifted right by 12 = 0x3, that is page 3.
Look up page 3 in the page table. Suppose it maps to frame 0x00A (frame number 10).
Physical address = frame number shifted left by 12, combined with the offset = 0x0000A000 combined with 0xF7C = 0x0000AF7C.
The offset 0xF7C carried straight through; only the top bits changed from page 3 to frame 10. That is the entire translation, and the exam gives it to you exactly this way.
Effective memory access time
With a TLB, the average cost of a memory reference is a weighted sum of the hit and miss paths. Let the TLB access time be 10 ns, main memory access be 100 ns, and the TLB hit ratio be 0.9.
TLB hit (probability 0.9): 10 ns for the TLB plus 100 ns for the data = 110 ns.
TLB miss (probability 0.1): 10 ns for the TLB, 100 ns to read the page table, then 100 ns for the data = 210 ns.
Effective access time = 0.9 × 110 + 0.1 × 210 = 99 + 21 = 120 ns. The same weighted-average method gives cache effective access time: EMAT = hit ratio × cache time + miss ratio × memory time. This one formula, applied to the TLB, the cache, or paging, answers most access-time numericals.
How the memory hierarchy is tested in GATE, NET and placements
GATE CS loves the numericals: split a virtual address into page number and offset, compute page-table size, calculate effective access time with a given TLB or cache hit ratio, and count page faults for a reference string under a replacement policy. The address-translation worked above is the standard drill. Reinforce it inside the wider syllabus with the Computer Architecture learn module.
UGC NET Computer Science keeps it conceptual: define locality, explain a page fault, and describe the TLB's role. Placement interviews connect virtual memory to the cache memory mapping and hit ratio below it and to pipelining in computer architecture above it, since a pipeline stalls on every miss, and they tie paging to OS process synchronization and semaphores that guard shared page frames.
The short version
See memory as one hierarchy: each level caches the level below, and locality is what makes it fast. Virtual memory maps pages to frames through a page table, the TLB caches recent mappings, and translation only ever rewrites the page-number bits while the offset passes through. Practise splitting a virtual address by hand and computing effective access time with a hit ratio, because those are the exact exam numericals. For a GATE-depth COA and OS sequence with solved memory problems, GATE Guidance by Sanchit Sir is built for it.