Memory management is how the operating system decides where each process lives in physical memory and how a program's addresses get mapped to real hardware locations. Get the mapping right and many processes share one memory safely; get it wrong and you waste memory to fragmentation or crash into another process. This topic is a reliable source of numerical questions, and almost all of them come down to one skill: translating a logical address into a physical one.
Why memory management is hard: contiguous allocation and fragmentation
The simplest scheme gives each process one contiguous block of physical memory. It is easy to translate addresses, but it fragments badly.
External fragmentation happens when free memory exists but is split into small scattered holes, none big enough for the next process even though their total is. Compaction can fix it by shuffling processes together, but that is expensive.
Internal fragmentation happens when a process is given a slightly larger fixed block than it needs, and the leftover inside the block is wasted.
Paging exists to kill external fragmentation outright, by dropping the requirement that a process occupy one contiguous block.
Paging: page tables, frames and address translation
Paging splits the logical address space into fixed-size pages and physical memory into frames of the same size. A process's pages can sit in any free frames, in any order. A per-process page table records which frame holds each page.
A logical address is split into two parts. The high bits are the page number, an index into the page table; the low bits are the offset within the page. Because pages and frames are the same size, the offset is copied straight through to the physical address, and only the page number is translated.
Work a concrete example. Let the page size be 4 KB, which is 4096 bytes, so the offset is 12 bits. Suppose this page table:
Page | Frame |
|---|---|
0 | 8 |
1 | 3 |
2 | 5 |
3 | 9 |
Translate logical address 8196.
Page number is 8196 divided by 4096, which is 2. Offset is 8196 minus 2 times 4096, which is 4.
Page 2 maps to frame 5 in the table.
Physical address is frame times page size plus offset: 5 times 4096 plus 4, which is 20484.
That is the entire mechanism. Every paging numerical is a variation on this split-lookup-combine procedure, and the memory management learn module has more of them to hand-solve.
The TLB: making translation fast
Every memory access now needs a page-table lookup, and the page table itself lives in memory, so a naive scheme doubles memory traffic. The translation lookaside buffer, or TLB, is a small fast cache of recent page-to-frame mappings. On a TLB hit the frame is found immediately; on a TLB miss the system reads the page table in memory and then loads the mapping into the TLB.
The effective memory access time is the weighted average of those two paths. Take a TLB lookup as 20 ns, one main-memory access as 100 ns, and a hit ratio of 90 percent. A hit costs 20 plus 100, which is 120 ns. A miss costs 20 for the failed TLB lookup, 100 to read the page table and 100 to read the data, which is 220 ns. The effective time is 0.9 times 120 plus 0.1 times 220, that is 108 plus 22, or 130 ns. Push the hit ratio to 99 percent and it falls to 121 ns, which is why a small TLB is worth so much silicon.
Multilevel page tables
A flat page table for a large address space is itself huge. A 32-bit space with 4 KB pages needs 2 to the power 20 entries per process, and at 4 bytes an entry that is 4 MB of contiguous page table for every process, most of it never touched. Multilevel paging pages the page table itself: an outer table points to inner tables, and only the inner tables you actually use are kept in memory. In the standard 32-bit case the 12-bit offset leaves a 20-bit page number, split 10 bits outer and 10 bits inner, so each table holds 1024 entries of 4 bytes and fits exactly in one 4 KB page. The price is one extra memory lookup per translation, which is why the TLB matters so much.
Segmentation vs paging
Segmentation divides a program by its logical structure rather than fixed size: a code segment, a stack segment, a data segment, each of variable length. An address is a segment number plus an offset, and a segment table stores each segment's base and limit.
Translation here is a bounds check rather than a fixed-size lookup. Suppose segment 2 has base 4300 and limit 400. Logical address (2, 53) is legal, because 53 is below the limit, and lands at 4300 plus 53, which is 4353. Logical address (2, 612) fails the check and traps. The limit field gives per-segment protection for free, which fixed-size pages cannot express.
Paging | Segmentation | |
|---|---|---|
Division | Fixed-size pages | Variable-size logical segments |
Visible to programmer | No | Yes |
Fragmentation | Internal | External |
Address form | Page number + offset | Segment number + offset |
Paging removes external fragmentation but has no relation to program meaning; segmentation matches program structure but brings external fragmentation back. Real systems often combine them as segmented paging, paging each segment so segments stay meaningful while frames stay fixed.
Paging in OS vs the memory hierarchy in computer organisation
Two neighbouring topics share the same vocabulary and are easy to confuse. Page tables, the TLB, and turning a logical address into a physical one are operating-systems material. The speed-and-cost hierarchy of registers, cache, main memory and disk, together with demand paging, page faults and page-replacement algorithms, belongs to computer organisation and virtual memory, and our memory hierarchy and virtual memory deep-dive covers that side. The two meet at the TLB, a hardware cache doing an operating-system job, so it repays learning from both directions.
How this is tested in GATE
Memory management alone carries over 220 questions in the KnowledgeGate question bank, part of close to 2,000 across operating systems. GATE overwhelmingly tests the numerical: given a page size and a logical address, find the physical address; given a hit ratio and access times, find the effective memory access time; given an address-space and page size, find the page-table size or the number of bits in each field. Conceptual questions ask you to compare paging and segmentation or to name which fragmentation each one causes. All of it follows from the translation mechanism above.
The short version
A logical address is a page number plus an offset. Translate the page number through the page table to a frame, carry the offset through unchanged, and combine. Paging fixes external fragmentation, segmentation matches program structure, and the TLB is what keeps translation fast. Hand-solve two or three translation problems and the numericals stop being scary.
Drill the exam forms on our operating systems memory management and paging MCQs, and time yourself on the effective-access-time sums until the arithmetic is automatic.
The full syllabus in order lives in GATE Guidance by Sanchit Sir, and more explainers on the CS Fundamentals category.
