Hardwired and microprogrammed control-unit questions look theoretical until you face a 26-bit split, a binary micro-operation or a vertical-encoding saving. Attempt each item before reading its answer. Five of the twelve turn on one habit: count the alternatives first, then take ceil(log2) of that count, never the other way round. The other seven test a definition, the speed order, or whether you can read a micro-operation sequence without updating a register early. The subtopic carries about 50 questions in those two moulds. GATE Guidance by Sanchit Sir gives the full Computer Architecture learning path, and every question heading links to that question's solved page.
1. Hardwired versus microprogrammed control: meaning, width and speed
Design | Control method | Main trade-off |
|---|---|---|
Hardwired | Fixed logic | Fastest, difficult to modify |
Horizontal | Wide, direct control bits | Parallel signals, little decoding |
Vertical | Narrow, encoded fields | More decoding, slowest |
The speed order is hardwired, horizontal, vertical. Control-signal generation meets datapath timing in Pipelining in Computer Architecture: Speedup and Hazards.
Q1 (ISRO 2018)
Micro program is
(a) the name of a source program in micro computers
(b) set of micro instructions that defines the individual operations in response to a machine-language instruction
(c) a primitive form of macros used in assembly language programming
(d) a very small segment of machine code
Answer: (b). A machine instruction such as ADD is realised internally as an ordered set of microinstructions that assert datapath control signals. The other choices confuse this sequence with a source program, an assembly macro or ordinary machine code.
Q2 (GATE 2002)
Horizontal microprogramming:
(a) does not require use of signal decoders
(b) results in larger-sized microinstructions than vertical microprogramming
(c) uses one bit for each control signal
(d) all of the above
Answer: (d). Direct control bits remove the decoder and permit one bit per signal, making the word wide. Statements (a), (b) and (c) are all correct, so (d) is complete.
Q3 (GATE 1999)
Arrange the following configurations for CPU in decreasing order of operating speeds; Hardwired Control, vertical microprogramming, horizontal microprogramming
(a) Hardwired control, Vertical microprogramming, Horizontal microprogramming.
(b) Hardwired control, Horizontal microprogramming, Vertical microprogramming.
(c) Horizontal microprogramming, Vertical microprogramming, Hardwired control.
(d) Vertical microprogramming, Horizontal microprogramming, Hardwired control.
Answer: (b). Hardwired logic avoids a control-memory access, so it leads. Horizontal microcode avoids much of vertical microcode's decoding overhead, giving Hardwired > Horizontal > Vertical.
2. Arithmetic micro-operations and sequential control words
Use three rules: a bar means bitwise complement, adding 1 forms the two's complement, and simultaneous transfers use old right-hand values. Keep CPU sequencing separate from control-memory sequencing.
Q4 (DSSSB 2021)
What is the meaning of this arithmetic micro-operation?
R3 ← R1 + R̅2 + 1
(a) Content of R1 plus R2 transferred to R3
(b) Content of R1 plus the 2’s complement of R2 transferred to R3
(c) Content of R1 plus the 1’s complement of R2 transferred to R3
(d) Content of R1 plus R2 after increments transferred to R3
Answer: (b). R̅2 is the one's complement of R2, and R̅2 + 1 is its two's complement. Thus the register-width operation computes R1 - R2 and transfers the result to R3.
Q5 (DSSSB 2021)
The 8-bit register A and B initially have the following values:
A = 01110110
B = 10000101
What is the 8-bit value in each register after execution of the following micro-operation?
A ← A + B
B ← B + 1
(a) A = 11111110, B = 10000101
(b) A = 11110111, B = 10001110
(c) A = 11111011, B = 10000110
(d) A = 11111101, B = 10000101
Answer: (c). A = 01110110 = 0x76 = 118 and B = 10000101 = 0x85 = 133. Therefore A becomes 118 + 133 = 251 = 0xFB = 11111011, while B becomes 133 + 1 = 134 = 0x86 = 10000110. Both right-hand sides use the initial values.
Q6 (UPPSC 2018)
Which one of the following is used to read the control words sequentially from the control memory?
(a) Microprogram address register
(b) Microprogram counter
(c) Control memory address register
(d) Program counter
Answer: (b). The microprogram counter advances the next microinstruction address in control memory. The program counter advances machine instructions in main memory, a different sequencing level.
3. Next-address fields and control-flow micro-operations
N status inputs need ceil(log2 N) MUX-select bits, and an X-bit next-address field reaches 2^X control-memory words. Size the fields you know first, then subtract them from the microinstruction width to get the one you do not.
Q7 (GATE 2004)
The microinstructions stored in the control memory of a processor have a width of 26 bits. Each microinstruction is divided into three fields: a micro-operation field of 13 bits, a next address field (X), and a MUX select field (Y). There are 8 status bits in the inputs of the MUX.
How many bits are there in the X and Y fields, and what is the size of the control memory in number of words?
(a) 10, 3, 1024
(b) 8, 5, 256
(c) 5, 8, 2048
(d) 10, 3, 512
Answer: (a). Eight status inputs need Y = log2 8 = 3 select bits. Then X = 26 - 13 - 3 = 10 bits, so the control memory has 2^10 = 1024 words.
Q8 (GATE 2013)
Consider the following sequence of micro-operations.
MBR ← PC
MAR ← X
PC ← Y
Memory ← MBR
Which one of the following is a possible operation performed by this sequence?
(a) Instruction fetch
(b) Operand fetch
(c) Conditional branch
(d) Initiation of interrupt service
Answer: (d). MBR receives the old PC, MAR selects X, PC becomes Y, and memory receives that old PC. Saving a return address while loading a service address initiates interrupt service, not an ordinary fetch.
4. Encoding micro-operations into compact control words
A field with k alternatives needs ceil(log2 k) bits. A no-operation code can raise the count to k + 1. Add independent field widths, following the question's convention.
Q9 (GATE 1996)
A microprogrammed control unit is required to generate a total of 25 control signals. Assume that during any microinstruction, at most two control signals are active. The minimum number of bits required in the control word to generate the required control signals will be _____.
(a) 2
(b) 2.5
(c) 10
(d) 12
Answer: (c). One active signal among 25 needs ceil(log2 25) = 5 bits. Two encoded selections need 5 + 5 = 10 bits, so two active signals do not mean a 2-bit word.
Q10 (UGC NET 2019)
A micro instruction format has microoperation field which is divided into 2 subfields 𝐹₁ and 𝐹₂ , each having 15 distinct microoperations, condition field CD for four status bits, branch field BR having four options used in conjunction with address field AD. The address space is of 128 memory words. The size of micro instruction is:
(a) 19
(b) 18
(c) 17
(d) 20
Answer: (a). Each F field represents 15 operations plus no-operation, so F1 = 4 bits and F2 = 4 bits. CD needs 2 bits, BR needs 2 bits, and AD for 128 words needs 7 bits. The total is 4 + 4 + 2 + 2 + 7 = 19 bits.
5. Horizontal versus vertical word-size calculations
Horizontal width counts direct signal bits; vertical width adds encoded group widths. A single-address horizontal word adds the next-address field, whose width also sets the control address register.
Q11 (GATE 2005)
An instruction set of a processor has 125 signals which can be divided into 5 groups of mutually exclusive signals as follows:
Group 1 : 20 signals, Group 2 : 70 signals, Group 3 : 2 signals, Group 4 : 10 signals, Group 5 : 23 signals.
How many bits of the control words can be saved by using vertical microprogramming over horizontal microprogramming?
(a) 0
(b) 103
(c) 22
(d) 55
Answer: (b). Horizontal width is 125 bits. The vertical widths are ceil(log2 20) = 5, ceil(log2 70) = 7, ceil(log2 2) = 1, ceil(log2 10) = 4 and ceil(log2 23) = 5, totalling 22 bits. The saving is 125 - 22 = 103 bits.
Q12 (GATE 2008)
Consider a CPU where all the instructions require 7 clock cycles to complete execution. There are 140 instructions in the instruction set. It is found that 125 control signals are needed to be generated by the control unit. While designing the horizontal microprogrammed control unit, single address field format is used for branch control logic. What is the minimum size of the control word and control address register?
(a) 125, 7
(b) 125, 10
(c) 135, 7
(d) 135, 10
Answer: (d). The control store needs 140 x 7 = 980 words. Since 2^9 = 512 < 980 and 2^10 = 1024 >= 980, the control address register and the word's own address field are each 10 bits. The control word needs 125 + 10 = 135 bits.
6. Control unit question patterns: the first move and the usual trap
Question pattern | First move | Trap |
|---|---|---|
Horizontal or vertical comparison | Identify direct and encoded fields | Reversing the speed order |
Micro-operation | Evaluate complements and old right-hand sides | Updating one register early |
Status MUX | Compute ceil(log2 inputs) | Using the number of inputs as bits |
Control-store size | Multiply instructions by cycles, then take the ceiling power of two | Confusing words with address bits |
Keep four anchors: 8 inputs need 3 select bits, 128 words need 7 address bits, 980 words need 10 address bits, and two selections among 25 signals need 10 bits. Do not confuse control-store addresses with the fields in Cache Memory: Mapping Techniques and Hit Ratio. Control memory also sits outside the main-memory, cache and virtual-memory hierarchy explained in Memory Hierarchy and Virtual Memory: Paging and TLB.
7. The short version and the next practice step
Three decisions solve most of the set: hardwired is fastest, horizontal is wider but less decoded than vertical, and field sizing starts by counting alternatives before ceil(log2). Redo all 12 with the answers covered, check each one through its question link, then work through the nearly 40 that remain on the subtopic.
Use GATE CS Exam Preparation Courses & Test Series for the broader route, or GATE Guidance by Sanchit Sir for sequenced Computer Architecture. If control unit design is the only weak area, work the question links along with the pipelining, cache mapping and memory hierarchy posts before committing to a full course.
