Demand-paging definitions look easy, but GATE questions on the topic combine virtual-page counts, page-table entry width, fault probability and millisecond-to-nanosecond conversions. One wrong unit can spoil an otherwise correct method. The twelve GATE questions below span 1997 to 2025. Attempt each one before reading its solution. Every question heading opens the demand-paging practice set, which holds over sixty previous-year questions in all, so save that click until you have committed to an option. Set aside an unbroken hour inside your wider GATE CS Exam Preparation, and begin without notes.
1. Demand paging basics: the four rules these numericals turn on
Check | Rule |
|---|---|
Page offset |
|
Virtual page count |
|
Page-table size |
|
Effective access time |
|
For M = 100 ns, D = 5 ms = 5,000,000 ns and p = 2 x 10^-6, E = (1 - 0.000002)(100) + (0.000002)(5,000,000) = 99.9998 + 10 = 109.9998 ns, about 110 ns. Convert D first to keep one unit.
A TLB miss adds page-table accesses; a page fault fetches from secondary storage. A dirty victim may need write-back. If any of those three paths is still hazy, the operating-system lectures in GATE Guidance by Sanchit Sir rebuild them before you take on the numericals.
2. Demand paging MCQs 1-3: locality, virtual-memory claims and swap space
Question 1, GATE 1997, Computer Science
Locality of reference implies that the page reference being made by a process:
A.
will always be to the page used in the previous page referenceB.
is likely to be to one of the pages used in the last few page referencesC.
will always be to one of the pages existing in memoryD.
will always lead to a page fault
Answer: B. Locality makes a page likely to recur within a recent working set, not necessarily immediately. All three always options fail; locality lets an active subset stay resident.
Question 2, GATE 2001, Computer Science
Which of the following statements is false?
A.
Virtual memory implements the translation of a program's address space into physical memory address spaceB.
Virtual memory allows each program to exceed the size of the primary memoryC.
Virtual memory increases the degree of multiprogrammingD.
Virtual memory reduces the context switching overhead
Answer: D. Address translation, space beyond RAM and more partially resident processes are valid capabilities. Page-table and translation-cache state add work, so lower context-switch overhead is not promised.
Question 3, GATE 2005, Computer Science
What is the swap space in the disk used for?
A.
Saving temporary html pagesB.
Saving process dataC.
Storing the super-blockD.
Storing device drivers
Answer: B. Swap backs pages or process data moved out of RAM. Browser cache, super-block metadata and driver files are unrelated.
3. Page-table MCQs 4-6: status bits, entry counts and table size
Question 4, GATE 2008, Computer Science, Information Technology
Match the following page table bits used in virtual memory management with their correct functions.
List I (Page Table Bit) | List II (Function) |
|---|---|
I. Dirty bit | a. Indicates whether the page has been modified and must be written back to disk |
II. R/W bit | b. Controls access permissions (read/write protection) |
III. Reference bit | c. Used by page replacement algorithms to track page usage |
IV. Valid bit | d. Indicates whether the page is currently present in main memory |
Choose the correct matching.
A.
I-d, II-a, III-b, IV-cB.
I-b, II-c, III-a, IV-dC.
I-c, II-d, III-a, IV-bD.
I-a, II-b, III-c, IV-d
Answer: D. Dirty means write-back, R/W protection, reference recent use, and valid presence. A clear valid bit causes a fault; dirty decides whether eviction needs a write.
Question 5, GATE 2025, Computer Science, Set 1
Consider a demand paging memory management system with 32-bit logical address, 20-bit physical address, and page size of 2048 bytes. Assuming that the memory is byte addressable, what is the maximum number of entries in the page table?
A.
2²¹B.
2²⁰C.
2²²D.
2²⁴
Answer: A, 2^21. Since 2048 bytes = 2^11 bytes, the page number has 32 - 11 = 21 bits and 2^21 values. Physical-address width affects the frame field, not entry count.
Question 6, GATE 2001, Computer Science
Consider a machine with 64 MB physical memory and a 32-bit virtual address space. If the page size is 4 KB, what is the approximate size of the page table?
A.
16 MBB.
8 MBC.
2 MBD.
24 MB
Answer: C, 2 MB. 2^32 / 2^12 = 2^20 virtual pages and 2^26 / 2^12 = 2^14 frames, so the frame number needs 14 bits. Approximating it as a 2-byte PTE gives 2^20 x 2 bytes = 2^21 bytes = 2 MB.
4. Effective access-time MCQs 7-10: fault cost, hit ratio and page-fault rate
Question 7, GATE 1998, Computer Science
If an instruction takes i microseconds and a page fault takes an additional j microseconds, the effective instruction time if, on average, a page fault occurs every k instructions is:
A.
i + j/kB.
i + j * kC.
(i + j)/kD.
(i + j) * k
Answer: A, i + j/k. Every instruction pays i; one fault cost j is spread over k instructions. Dividing (i+j) by k wrongly removes ordinary cost.
Question 8, GATE 2000, Computer Science
Suppose the time to service a page fault is on the average 10 milliseconds, while a memory access takes 1 microsecond. Then a 99.99% hit ratio results in average memory access time of?
A.
1.9999 millisecondsB.
1 millisecondC.
9.999 microsecondsD.
1.9999 microseconds
Answer: D, 1.9999 microseconds. 10 ms = 10,000 microseconds; hit ratio 0.9999 means fault ratio 0.0001. Thus 0.9999 x 1 + 0.0001 x 10,000 = 0.9999 + 1 = 1.9999 microseconds; the tiny rate matters because faults are four orders slower.
Question 9, GATE 2018, Computer Science
Consider a process executing on an operating system that uses demand paging. The average time for a memory access in the system is M units if the corresponding memory page is available in memory, and D units if the memory access causes a page fault. It has been experimentally measured that the average time taken for a memory access in the process is X units.
Which one of the following is the correct expression for the page fault rate experienced by the process?
A.
(D - M) / (X - M)B.
(X - M) / (D - M)C.
(D - X) / (D - M)D.
(X - M) / (D - X)
Answer: B. X = (1-p)M + pD = M + p(D-M), so p = (X-M)/(D-M). The range check gives zero at X=M and one at X=D.
Question 10, GATE 2011, Computer Science
Let the page fault service time be 10 milliseconds(ms) in a computer with average memory access time being 20 nanoseconds (ns). If one page fault is generated every 10^6 memory accesses, what is the effective access time for memory?
A.
21 nsB.
30 nsC.
23 nsD.
35 ns
Answer: B, 30 ns. With 10 ms = 10,000,000 ns and p = 10^-6, (1-p)20 + p(10,000,000) = 19.99998 + 10 = 29.99998 ns, about 30 ns. Missing the conversion hides the 10 ns fault contribution.
5. Demand paging MCQs 11-12: trace loaded ranges and combine TLB with fault cost
Question 11, GATE 2007, Computer Science, Information Technology
The address sequence generated by tracing a particular program executing in a pure demand paging system with 100 bytes per page is
0100, 0200, 0430, 0499, 0510, 0530, 0560, 0120, 0220, 0240, 0260, 0320, 0410.
Suppose that the memory can store only one page and if x is the address which causes a page fault then the bytes from addresses x to x + 99 are loaded on to the memory.
How many page faults will occur ?
A.
0B.
4C.
7D.
8
Answer: C, 7. The unaligned rule loads 0100-0199, 0200-0299, 0430-0529, 0530-0629, 0120-0219, 0220-0319 and 0320-0419; intervening references hit. The faults are 0100, 0200, 0430, 0530, 0120, 0220, 0320, not eight from forced alignment.
Question 12, GATE 2004, Computer Science
Consider a system with a two-level paging scheme in which a regular memory access takes 150 nanoseconds, and servicing a page fault takes 8 milliseconds. An average instruction takes 100 nanoseconds of CPU time, and two memory accesses. The TLB hit ratio is 90%, and the page fault rate is one in every 10,000 instructions. What is the effective average instruction execution time?
A.
645 nanosecondsB.
1050 nanosecondsC.
1215 nanosecondsD.
1260 nanoseconds
Answer: D, 1260 nanoseconds. A hit costs 150 ns, a miss 3 x 150 = 450 ns, so one reference averages 0.9 x 150 + 0.1 x 450 = 180 ns and base time is 2 x 180 + 100 = 460 ns. Faults add (1/10,000) x 8,000,000 ns = 800 ns, giving 460 + 800 = 1260 ns.
6. Demand paging traps: audit the unit, probability and address field
Mistake | What goes wrong |
|---|---|
Use hit ratio as fault ratio | Wrong weights |
Mix milliseconds and nanoseconds | Questions 8, 10 and 12 fail |
Count virtual pages from physical bits | Question 5 fails |
Align despite | Question 11 changes from 7 to 8 |
Audit afterwards: time lies between hit and fault paths, probability in [0,1], and entries follow logical pages. Dirty affects eviction; valid records presence. Which page the system evicts once every frame is full is the next question, answered in Page Replacement Algorithms for GATE: FIFO, LRU and Optimal with Belady's Anomaly Explained.
7. Demand paging MCQs: the short version and next practice step
Diagnose misses: Questions 1-4 test vocabulary and bits, 5-6 address decomposition, 7-10 and 12 probability and units, and 11 whether you followed the loading rule the question states, x to x + 99, instead of the aligned 100-byte page you expect.
Next, attempt Virtual Memory and Demand Paging MCQs: 12 Solved Questions with Explanations. Reattempt misses after 48 hours, then use the GATE Test Series for timed mixed-topic practice.
