Paging and TLB MCQs: 12 Solved Questions with Step-by-Step Explanations

Paging questions mix address-bit splits, page-table sizing, and TLB timing. Attempt each option before reading its explanation. The earlier memory-management and paging MCQ set uses five of these questions inside a mixed allocation, paging and demand-paging review. Here, those five anchor a calculation-heavy sequence with seven additional questions on address widths, page-table size, TLB coverage, timing and fragmentation.

1. Page-table essentials before the numericals

Q1. Page-table entry content, GATE 2009

The essential content(s) in each entry of a page table is / are?

• A. Virtual page number

• B. Page frame number

• C. Both virtual page number and page frame number

• D. Access right information

Answer: B. Page frame number. The virtual page number indexes the page table; the selected entry supplies the physical frame number. Joining it to the unchanged offset forms the physical address. Protection bits may accompany the mapping, but the frame number is essential. The trap is storing the index instead of the mapping. See the full solution.

Q2. Why one-level paging becomes impractical, GATE 2003

In a system with 32-bit virtual addresses and 1 KB page size, use of one-level page tables for virtual to physical address translation is not practical because of

• A. the large amount of internal fragmentation

• B. the large amount of external fragmentation

• C. the large memory overhead in maintaining page tables

• D. the large computation overhead in the translation process

Answer: C. the large memory overhead in maintaining page tables. A 1 KB page is 2^10 bytes, giving a 10-bit offset and a 32 - 10 = 22-bit virtual page number. A flat table therefore needs 2^22 entries per process. No entry size is given, but this count proves the storage overhead. See the full solution.

2. Address bits and page-table size

Use one rule: address bits = selector bits + offset bits. Page size gives the offset; page or frame count gives the selector.

Q3. Logical and physical address widths, UGC NET 2017

A memory management system has 64 pages with 512 bytes page size. Physical memory consists of 32 page frames. Number of bits required in logical and physical address are respectively :

• A. 14 and 15

• B. 14 and 29

• C. 15 and 14

• D. 16 and 32

Answer: C. 15 and 14. With 64 = 2^6 pages and 512 = 2^9 bytes per page, the logical address needs 6 + 9 = 15 bits. Physical memory has 32 = 2^5 frames, so its address needs 5 + 9 = 14 bits. Translation changes the selector, but the 9-bit offset stays unchanged. See the full solution.

Q4. Single-level page-table size, UGC NET 2021

Consider a machine with 16 GB of main memory, a 32-bit virtual address space, and a 4 KB page size. Frame size equals page size. What is the size of the page table for this virtual address space if each page-table entry is 2 bytes?

• A. 2MB

• B. 2KB

• C. 32MB

• D. 12KB

Answer: A. 2MB. A 4 KB page is 2^12 bytes, so the virtual space has 2^(32-12) = 2^20 pages. The table size is 2^20 entries × 2 bytes = 2^21 bytes = 2 MB. The 16 GB physical-memory value is not needed for this virtual page-table calculation. See the full solution.

3. PTE metadata and the page-size trade-off

Q5. Bits left in a page-table entry, GATE 2004

In a virtual memory system, size of virtual address is 32-bit, size of physical address is 30-bit, page size is 4 Kbyte and size of each page table entry is 32-bit. The main memory is byte addressable. Which one of the following is the maximum number of bits that can be used for storing protection and other information in each page table entry?

• A. 2

• B. 10

• C. 12

• D. 14

Answer: D. 14. A 4 KB page gives a 12-bit offset. The 30-bit physical address therefore needs 30 - 12 = 18 frame-number bits. A 32-bit PTE leaves 32 - 18 = 14 bits for protection and other information. See the full solution.

Q6. Optimum page size, UGC NET 2014

For the implementation of a paging scheme, suppose the average process size be x bytes, the page size be y bytes, and each page entry requires z bytes. The optimum page size that minimizes the total overhead due to the page table and the internal fragmentation loss is given by

• A. x/2

• B. xz/2

• C. sqrt(2xz)

• D. sqrt(xz)/2

Answer: C. sqrt(2xz). Table overhead is (x/y)z = xz/y, while average internal fragmentation is y/2. Thus overhead(y) = xz/y + y/2. Its derivative is -xz/y^2 + 1/2. Setting it to zero gives y^2 = 2xz, so the meaningful positive root is y = sqrt(2xz). See the full solution.

4. TLB set, tag, and coverage arithmetic

Split the virtual page number as VPN = TLB tag + set index; the offset bypasses tag comparison. For coverage, track the machine's addressable unit.

Q7. Minimum TLB tag width, GATE 2006

A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. What is the minimum size of the TLB tag?

• A. 11 bits

• B. 13 bits

• C. 15 bits

• D. 20 bits

Answer: C. 15 bits. A 4 KB page gives a 12-bit offset and a 20-bit VPN. The TLB has 128/4 = 32 = 2^5 sets, requiring a 5-bit index. Thus tag width = 20 - 5 = 15 bits; the four ways share the selected set. See the full solution.

Q8. Maximum addresses covered without a TLB miss, GATE 2019

Assume that in a certain computer, the virtual addresses are 64 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 8kB and the word size is 4 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 128 valid entries. At most how many distinct virtual addresses can be translated without any TLB miss?

• A. 16 x 2^10

• B. 256 x 2^10

• C. 4 x 2^20

• D. 8 x 2^20

Answer: B. 256 x 2^10. Each page has 8192/4 = 2048 = 2^11 word addresses. With 128 = 2^7 entries, coverage is 2^7 × 2^11 = 2^18 = 256 × 2^10 word addresses. Address widths do not alter this count; counting bytes is the trap. See the full solution.

5. Effective access time with a TLB

Here lookup is serial with memory access. A hit costs TLB plus one memory access; a miss without a page fault adds a page-table memory access.

Q9. Weighted TLB hit and miss time, GATE 2008

A paging scheme uses a Translation Look-aside Buffer (TLB). A TLB access takes 10 ns and a main memory access takes 50 ns. What is the effective access time (in ns) if the TLB hit ratio is 90% and there is no page fault?

• A. 54

• B. 60

• C. 65

• D. 75

Answer: C. 65. Hit time = 10 + 50 = 60 ns. Miss time = 10 + 50 + 50 = 110 ns. Therefore EAT = 0.9(60) + 0.1(110) = 54 + 11 = 65 ns. The 60 ns option is only the hit path; a TLB miss is not a page fault. See the full solution.

For drills where a missing page does trigger secondary-storage service, continue with the virtual-memory and demand-paging MCQ set.

6. Statement traps and page-fault-scale timing

Q10. The false address-translation statement, GATE 2022

Which one of the following statements is FALSE?

• A. The TLB performs an associative search in parallel on all its valid entries using page number of incoming virtual address.

• B. If the virtual address of a word given by CPU has a TLB hit, but the subsequent search for the word results in a cache miss, then the word will always be present in the main memory.

• C. The memory access time using a given inverted page table is always same for all incoming virtual addresses.

• D. In a system that uses hashed page tables, if two distinct virtual addresses V1 and V2 map to the same value while hashing, then the memory access time of these addresses will not be the same.

Answer: C. Statement C claims that access time through a given inverted page table is the same for every incoming virtual address. An inverted table is searched rather than indexed directly, so different addresses can need different amounts of scanning before their entry is found, and that is what makes the word always wrong here. Contrast it with the TLB's parallel associative comparison in A, which does treat all valid entries alike. See the full solution.

Q11. Average time when rare page faults dominate, TPSC 2025

Suppose the time to service a page fault is on average 10 milliseconds, while a memory access takes 1 microsecond. Then a 99.99% hit ratio results in an average memory access time of

• A. 1.9999 milliseconds

• B. 1.1 milliseconds

• C. 9.999 microseconds

• D. 2 microseconds

Answer: D. 2 microseconds. Convert 10 ms to 10,000 microseconds. Page-fault probability = 1 - 0.9999 = 0.0001. Average time = 0.9999(1) + 0.0001(10,000) = 1.9999 microseconds, which rounds to 2 microseconds. This is a page-fault ratio, unlike Q9's TLB-hit ratio. See the full solution.

7. Internal fragmentation check and what to practise next

Q12. Internal-fragmentation percentage, TPSC 2024

In a paging system with internal fragmentation, a process requires 7KB of memory, but is allocated a full 8KB page frame. What is the internal fragmentation percentage?

• A. 12.5%

• B. 25%

• C. 50%

• D. 75%

Answer: A. 12.5%. Waste = 8 KB - 7 KB = 1 KB. Using allocated space as the denominator, fragmentation = (1/8) × 100 = 12.5%. Dividing by the 7 KB request is the trap. See the full solution.

Remember four moves: derive the offset from page size, calculate page and frame selectors separately, count TLB sets before splitting index and tag, then weight the hit and miss paths.

If these calculations felt slow, review GATE Guidance by Sanchit Sir, use the GATE course and test-series category for timed practice, then try the page-replacement algorithms MCQ set.