Carry Look-Ahead Adder (CLA) and Arithmetic Logic: Equations, Worked Examples and Exam Questions

A ripple-carry adder is easy to draw, but CLA questions become confusing when bit order, P_i, G_i, carry equations, two's-complement subtraction, and overflow appear together. Carry look-ahead addition uses one notation system from a one-bit full adder through a complete four-bit addition, then applies it to an add-subtract circuit and exact overflow checks. Derive a carry equation instead of memorising it, calculate the result, and distinguish carry-out from signed overflow.

Related reading: Adders and subtractors and Combinational circuits.

1. Arithmetic logic starts with one full-adder bit

Number bits from i=0 at the least significant bit to i=3 at the most significant bit. C_i enters bit i; C_{i+1} leaves it. In Boolean equations, + means OR, adjacency means AND, and XOR means exclusive OR, not arithmetic addition.

A half adder gives S=A XOR B and C=AB. An input carry produces the full-adder equations:

S_i=A_i XOR B_i XOR C_i

C_{i+1}=A_iB_i+(A_i XOR B_i)C_i

For A_i=1, B_i=0, and C_i=1, the arithmetic total is 2, so the output is sum 0, carry 1. Arithmetic logic belongs inside the wider Digital Logic preparation covered by GATE CS Exam Preparation.

2. Ripple carry versus carry look-ahead

A four-bit ripple adder chains full adders through C_1, C_2, and C_3. Bit 3 waits for the lower carries. If each stage hypothetically needs 2 ns after receiving its carry, C_0 to C_4 takes 4 x 2 = 8 ns. This is not a universal hardware delay.

CLA starts by defining XOR-propagate and generate:

P_i=A_i XOR B_i and G_i=A_iB_i

G_i=1 creates a carry regardless of C_i; P_i=1 passes C_i onward. The full-adder equation becomes C_{i+1}=G_i+P_iC_i. CLA uses the original P, G, and C_0 inputs instead of waiting serially. Gate depth, fan-in, wiring, and hierarchy still cause delay. See Combinational Circuits: MUX, Decoders, Adders for truth tables and hardware roles across MUXes, decoders, and adders; the CLA treatment here focuses on parallel carry equations and block propagation.

3. Derive every four-bit CLA carry equation

Begin with C_1=G_0+P_0C_0. Now substitute it into the next recurrence:

C_2=G_1+P_1C_1

C_2=G_1+P_1(G_0+P_0C_0)=G_1+P_1G_0+P_1P_0C_0

Continuing the same expansion gives:

• C_3=G_2+P_2G_1+P_2P_1G_0+P_2P_1P_0C_0

• C_4=G_3+P_3G_2+P_3P_2G_1+P_3P_2P_1G_0+P_3P_2P_1P_0C_0

The sum remains S_i=P_i XOR C_i. Look-ahead changes carry calculation, not the arithmetic definition of the sum.

For the whole block, define P_G=P_3P_2P_1P_0 and G_G=G_3+P_3G_2+P_3P_2G_1+P_3P_2P_1G_0. Therefore, C_4=G_G+P_GC_0.

Some sources use A_i+B_i as propagate for carry-only reasoning. Here it is A_i XOR B_i, which supports S_i=P_i XOR C_i. Never mix the conventions.

4. Four-bit CLA worked example: 1011 + 0110

Let A=1011 (11 unsigned), B=0110 (6 unsigned), and C_0=0. Words are written most significant bit first, but calculate from i=0.

Evaluate the look-ahead expressions: C_1=0; C_2=G_1=1; C_3=G_2+P_2G_1=0+1(1)=1; and C_4=G_3+P_3G_2+P_3P_2G_1=0+1(0)+1(1)(1)=1. Every term containing C_0=0 vanishes.

Read back S_3S_2S_1S_0=0001. With C_4=1, the result is 10001_2=17, matching 11+6=17. Also, P_G=1(1)(0)(1)=0 and G_G=0+1(0)+1(1)(1)+1(1)(0)(0)=1, so C_4=1+0(C_0)=1.

5. Group propagate and generate for larger adders

P_G=1 means every bit in the block propagates its input carry to the output. G_G=1 means the block creates an output carry even when its input carry is 0. Above, P_G=0 and G_G=1, so the block creates C_4=1 independently of C_0.

For a hypothetical 16-bit hierarchy, use four four-bit blocks numbered low to high. Let their (P_G,G_G) values be (1,0), (1,0), (0,1), (1,0), with K_0=1. The block recurrence gives K_1=0+1(1)=1, K_2=0+1(1)=1, K_3=1+0(1)=1, and K_4=0+1(1)=1.

Expanded equations become wide and expensive, so practical designs use block look-ahead levels or other prefix structures.

6. Add-subtract logic and exact overflow checks

In a four-bit add-subtract path, use B_i^*=B_i XOR M and C_0=M. Then M=0 gives A+B; M=1 gives A+B'+1=A-B in two's complement. Refresh representation with Number Systems and Base Conversions: GATE Worked Examples.

For A=0101 (5) and B=0010 (2):

For unsigned subtraction, discard C_4; here C_4=1 means no borrow.

Carry-out is not signed overflow. Four-bit signed 0111 (+7) plus 0011 (+3) produces 1010. The carry into the sign bit is C_3=1, while C_4=0, so V=C_3 XOR C_4=1. Two positive inputs produced a negative-sign result. By contrast, 1111+0001=1 0000 has C_3=1 and C_4=1, so V=0; as signed values, -1+1=0 is valid.

7. Representative CLA exam questions and traps

Solve each pattern by keeping the bit width fixed, expanding carries from i=0, and checking whether the question asks for carry-out or signed overflow.

1. Given P_3P_2P_1P_0=1101, G_3G_2G_1G_0=0010, and C_0=0, find C_4. Substitution gives 0+1(0)+1(1)(1)=1.

2. In the hypothetical ripple model above, four carry stages at 2 ns each give 8 ns. That result belongs only to the stated model.

3. For 0111+0011=1010, carry-out is 0, while signed overflow is 1.

4. With M=1, forgetting the B inversion or C_0=1 breaks subtraction. 0101+1101 truncates to 0010, not 0011.

Use Combinational Circuits MCQs: 12 Solved GATE Questions as timed follow-on practice.

8. Carry look-ahead and arithmetic logic: the short version

Keep this recall card:

• P_i=A_i XOR B_i

• G_i=A_iB_i

• C_{i+1}=G_i+P_iC_i

• S_i=P_i XOR C_i

• Four-bit signed overflow: V=C_3 XOR C_4

For controlled subtraction, B^*=B XOR M and C_0=M.

Now reproduce this without looking. For 1011+0110, P_3P_2P_1P_0=1101, G_3G_2G_1G_0=0010, carries C_1,C_2,C_3,C_4 are 0,1,1,1, and the result is 1 0001.

For a sequenced route through GATE CS preparation, continue with GATE Guidance by Sanchit Sir.