A positive edge-triggered D flip-flop is connected to a positive…
2015
A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.
- A.
0110110…
- B.
0100100…
- C.
011101110…
- D.
011001100…
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Correct answer: A
Answer: The JK flip-flop Q output is 0110110… (the 3-step pattern 0,1,1 repeats).
Reasoning (trace by rising clock edges, including initial state):
Initial state: D flip-flop Q = 1, JK flip-flop Q = 0.
Rising edge 1 (samples): D samples JK_Q = 0 → D_next = 0. JK samples J = K = D_Q = 1 → JK toggles 0 → 1. Resulting outputs after propagation: D_Q = 0, JK_Q = 1.
Rising edge 2 (samples): D samples JK_Q = 1 → D_next = 1. JK samples J = K = D_Q = 0 → JK holds (J = K = 0) so JK_Q remains 1. Result: D_Q = 1, JK_Q = 1.
Rising edge 3 (samples): D samples JK_Q = 1 → D_next = 1. JK samples J = K = D_Q = 1 → JK toggles 1 → 0. Result: D_Q = 1, JK_Q = 0.
Rising edge 4 (samples): D samples JK_Q = 0 → D_next = 0. JK samples J = K = D_Q = 1 → JK toggles 0 → 1. Result: D_Q = 0, JK_Q = 1.
Rising edge 5 (samples): D samples JK_Q = 1 → D_next = 1. JK samples J = K = D_Q = 0 → JK holds → JK_Q = 1. Result: D_Q = 1, JK_Q = 1.
Rising edge 6 (samples): D samples JK_Q = 1 → D_next = 1. JK samples J = K = D_Q = 1 → JK toggles 1 → 0. Result: D_Q = 1, JK_Q = 0.
From the JK outputs recorded (including the initial state) we get 0, 1, 1, 0, 1, 1, 0, … so the pattern 0,1,1 repeats. The finite propagation delays do not change the sampled inputs at the clock edge (both flip-flops are positive edge-triggered), so the above edge-by-edge sampling determines the sequence.
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