Programmed I/O MCQs: 10 Solved Questions on Polling, CPU Time and Bus Control

Programmed I/O questions reuse a small set of signals: polling, busy waiting, status flags, CPU-controlled transfer and wasted processor cycles. Numerical questions add two reliable moves: convert CPU cycles to time, and turn a minimum inter-arrival interval into a safe polling frequency. Recognise the control pattern before the options distract you. Use the GATE CS Exam Preparation path when revising Computer Architecture. Direct question pages are linked for Questions 1-5, 7 and 9. For Questions 6, 8 and 10, use the Programmed I/O practice hub.

Programmed I/O basics: who initiates and controls the transfer

In programmed I/O, the CPU executes instructions to read device status and transfer data. The processor stays in the control path, unlike interrupt-driven I/O or DMA.

Question 1: program instruction initiates the transfer

Source: DSSSB 2022

Which of the following data transfer modes between CPU and I/O devices has the data transfer initiated by the instruction of a computer program executed by the CPU?

• A. Programmed I/O mode

• B. Interrupt initiated I/O mode

• C. Direct Memory Access (DMA) mode

• D. Direct Register Access (DRA) mode

Answer: A. Programmed I/O mode. The phrase “instruction of a computer program executed by the CPU” identifies programmed I/O. An interrupt signal starts interrupt service, while a DMA controller moves a block without continuous CPU participation.

Question 2: CPU stays in a readiness loop

Source: DSSSB 2022

In which of the following data transfer modes does the CPU constantly monitor the peripheral and stay in a program loop until the peripheral device becomes ready for data transfer?

• A. Direct Memory Access (DMA) mode

• B. Direct Register Access (DRA) mode

• C. Programmed I/O mode

• D. Interrupt initiated I/O mode

Answer: C. Programmed I/O mode. “Constantly monitor” and “program loop” mean busy waiting. The CPU repeatedly reads the status register until the ready bit changes, so those cycles cannot do unrelated work.

Question 3: the CPU-cycle cost

Source: DSSSB 2022

Which of the following statements about programmed I/O mode of data transfer between CPU and I/O devices is correct?

• A. The programmed I/O mode of data transfer is faster than interrupt mode of data transfer.

• B. In this mode, there is wastage of the CPU cycles.

• C. In this mode, the CPU can do other works when I/O devices are not ready for data transfer.

• D. In this mode, the data transfer is initiated by the interrupt signal issued to the CPU.

Answer: B. In this mode, there is wastage of the CPU cycles. Repeated status checks consume cycles even when no byte moves. Options C and D instead describe the advantage and trigger of interrupt-driven I/O.

Polling and status flags: three names for the same exam clue

Polling is the repeated action, busy waiting is the CPU behaviour, and program-controlled or programmed I/O is the transfer method.

Question 4: constant peripheral monitoring

Source: DSSSB 2018

Which of the following data transfer schemes requires constant monitoring by the CPU of the peripheral devices?

• A. Programmed IO

• B. Interrupt-driven IO

• C. Direct Memory Access (DMA)

• D. Both, Interrupt-driven IO and DMA

Answer: A. Programmed IO. Constant CPU monitoring defines programmed I/O. Interrupt-driven I/O signals readiness, while DMA delegates movement to a controller after setup.

Question 5: repeated status-flag checks

Source: BPSC 2023

The method of accessing the I/O devices by repeatedly checking the status flags is

• A. program-controlled I/O

• B. memory-mapped I/O

• C. I/O-mapped I/O

• D. More than one of the above

• E. None of the above

Answer: A. program-controlled I/O. Repeated checking is a control method. Memory-mapped and I/O-mapped I/O describe how device registers occupy and are addressed within address spaces.

Question 6: the one-word polling cue

Source: UP Police 2023. Programmed I/O practice in the learn module

Which type of I/O communication method requires the processor to check the device status repeatedly?

• A. Cache Coherency

• B. Polling

• C. Direct Memory Access

• D. Interrupt-driven I/O

Answer: B. Polling. Polling means periodic or continuous status-register reads by the processor. Cache coherency is unrelated, DMA uses a controller, and interrupt-driven I/O waits for a device signal.

All three questions reduce to one idea: the CPU repeatedly reads device status.

I/O connectivity and bus arbitration

Programmed I/O still uses an interface and shared buses. A question may therefore test the surrounding path without saying “busy waiting”.

Question 7: extending processor-bus connectivity

Source: BPSC 2023

What do we use to extend the connectivity of the processor bus?

• A. PCI bus

• B. Multiple bus

• C. SCSI bus

• D. More than one of the above

• E. None of the above

Answer: A. PCI bus. PCI is an expansion or peripheral bus that connects more devices through the system I/O structure. SCSI is mainly a peripheral interface standard, while “multiple bus” is not the named standard requested.

Question 8: simultaneous bus requests

Source: MPPSC 2025. Programmed I/O practice in the learn module

What happens if the CPU and an I/O controller want to use the bus at the same time? Who decides who goes next?

• A. DMA

• B. Interrupt handler

• C. Bus arbiter

• D. CPU

Answer: C. Bus arbiter. It receives competing requests and grants bus ownership under the system’s arbitration rule. DMA is a transfer mechanism and an interrupt handler is software, so neither grants the shared bus.

The path is CPU instruction to I/O interface or controller to peripheral. A bus arbiter chooses a requester only when contention occurs.

Programmed I/O numericals: CPU time and safe polling frequency

Question 9: CPU time for a 2,000-byte block

Source: UGC NET January 2026

A system transfers data blocks of 2000 bytes with programmed I/O, each byte transfer takes 6 CPU cycles. With direct memory access (DMA), the block transfer takes 3000 cycles total, with CPU setup overhead of 200 cycles. The CPU clock is 1 GHz.

How much CPU time is consumed by programmed I/O?

• A. 12 μs

• B. 20 μs

• C. 24 μs

• D. 30 μs

Answer: A. 12 μs.

1. Programmed-I/O cycles = 2,000 bytes x 6 cycles/byte = 12,000 cycles.

2. CPU time = 12,000 cycles / 10^9 cycles/s = 12 x 10^-6 s = 0.000012 s.

3. In microseconds, 0.000012 s x 10^6 μs/s = 12 μs.

The DMA figures are distractors because the question asks only for programmed-I/O CPU time.

Question 10: minimum polling rate for a one-character buffer

Practice set: Programmed I/O practice in the learn module

In programmed I/O, software can poll periodically and let the processor do other work between checks. A keyboard has a single-character buffer. Characters arrive at an average rate of 2 per second, but the minimum gap between two key presses is 100 ms. What is the minimum number of times per second the processor must check the buffer to ensure that no character is overwritten?

The answer is a number rather than an option letter.

Answer: 10 times per second. The average rate does not set the safety bound because consecutive key presses may be only 100 ms apart. A single-character buffer must be checked within 100 ms = 0.1 s, so the minimum frequency is 1 s / 0.1 s = 10 checks per second.

Programmed I/O comparison table and elimination rules

Use four quick elimination rules:

• “Program loop” or “repeatedly checks” means programmed I/O or polling.

• “Device signals CPU” means interrupt-driven I/O.

• “Controller transfers a block to memory” means DMA.

• “Two requesters want the bus” means bus arbitration.

How to revise the surrounding Computer Architecture topics

The cycle-to-time conversion in Question 9 also appears in Pipelining in Computer Architecture Explained. The distinction between transfer control and data location becomes useful when studying Cache Memory: Mapping and Hit Ratio.

Use one 15-minute loop: spend 5 minutes writing the Programmed I/O, interrupt and DMA comparison from memory; 5 minutes solving 2,000 x 6 / 10^9; and 5 minutes explaining why a 100 ms minimum gap requires 10 checks per second. Do not treat memory-mapped I/O as a polling method. Also, protect a one-character buffer with the minimum inter-arrival time, not the average arrival rate.

Programmed I/O MCQs: the short version and next step

Programmed I/O is CPU-controlled. Polling consumes processor cycles. Bus arbitration resolves contention. Careful units solve the numericals.

For a structured GATE preparation path, continue with GATE Guidance by Sanchit Sir. If you are revising core CS beyond one exam topic, use the broader Zero to Hero Complete CS Course.

Now reattempt the set without the explanations. Finish by writing one line that distinguishes programmed I/O, interrupts and DMA.