Hazards and Timing in Combinational Circuits: Worked Glitch Analysis and Exam Traps

Boolean algebra may say that an output remains 1 or 0, yet a real gate network can briefly show the opposite value because its paths do not settle together. Propagation delay and contamination delay bound when an output may change and when it is guaranteed stable; a hazard is a circuit condition that permits an unwanted transition, and a glitch is the pulse observed for a particular input change and delay assignment. For F=AB+A'C, exact gate delays produce a 2 ns static-1 glitch, a missing K-map overlap identifies the fault, and consensus term BC removes it without changing the steady-state function. The same timing vocabulary supports contamination and propagation bounds, safe clock checks, and exam-style classification.

Related reading: Boolean minimisation and logic circuit analysis.

Hazards in combinational circuits: correct logic can still glitch

A Boolean expression gives steady-state values, but physical gates also have delays. If one input reaches a final gate through reconvergent paths, unequal arrival times can make the intermediate output wrong even when both endpoints are correct.

A hazard is a circuit condition that permits an unwanted transition. A glitch is the pulse observed for a particular input change and delay assignment. A steady-state truth table cannot reveal it. Static-hazard analysis assumes one input changes at a time.

Broader Digital Logic practice sits in CS Fundamentals for Exams & Placements. For the parent circuit vocabulary, revise Combinational Circuits: MUX, Decoders, Adders.

Timing vocabulary: contamination delay, propagation delay and path bounds

Contamination delay, t_cd, is the earliest time after an input change when an output may begin changing. Propagation delay, t_pd, is the latest time by which it is guaranteed stable. Neither says the output is valid throughout the interval between them.

For A -> AND -> OR, t_cd=1+1=2 ns and t_pd=3+2=5 ns. For A -> NOT -> AND -> OR, t_cd=1+1+1=3 ns and t_pd=2+3+2=7 ns. The output may react after min(2,3)=2 ns and is settled by max(5,7)=7 ns. Add delays along each path, then take the minimum contamination sum and maximum propagation sum.

Static-1 hazard worked example: calculate the exact low pulse

Let F=AB+A'C, with P=AB, Q=A'C and Y=P+Q. Hold B=C=1. Initially A=1, giving P=1, Q=0, Y=1. At t=0, let A fall to 0. The new steady state remains Y=1, now through Q.

For this deterministic trace, treat the table's propagation delays as fixed transport delays: NOT 2 ns, AND 3 ns, OR 2 ns.

Both OR inputs are 0 from 3 ns to 5 ns, so the internal zero window is 5-3=2 ns. The OR transport delay shifts it without changing its width. Thus Y is low from 5 ns to 7 ns, another 2 ns window. It is a static-1 hazard because the intended output is 1 at both endpoints.

Remove the static-1 hazard with the consensus term

In variable order A,B,C, F=Sigma m(1,3,6,7). Group A'C covers m1,m3; AB covers m6,m7. Adjacent transition cells m3=011 and m7=111 have no overlapping implicant, exposing the hazard when only A changes.

Add the consensus term BC, which covers m3,m7:

F_h=AB+A'C+BC

With B=C=1, BC=1 throughout, so the OR gate never sees all inputs at 0. The implementation changes, but the function does not:

BC=BC(A+A')=ABC+A'BC

Because AB+ABC=AB and A'C+A'BC=A'C, AB+A'C+BC=AB+A'C. The earlier Advanced Boolean Laws and Optimization post owns algebraic simplification and circuit-cost trade-offs. Here, the consensus term serves a different purpose: it preserves the steady-state function while eliminating the delay-induced 2 ns glitch.

Static-0, dynamic and functional hazards: do not mix the categories

A static-0 hazard is the dual. For G=(A+B)(A'+C), hold B=C=0 and change A from 0 to 1. The ideal output is always 0, but unequal delays can briefly make both sum terms 1. Add the consensus sum: G_h=(A+B)(A'+C)(B+C). Since B+C=0 throughout, no high pulse can pass.

A dynamic hazard produces multiple transitions when the output should change once, usually in a multilevel network. One trace is 0 -> 1 -> 0 -> 1 at 2 ns, 4 ns and 6 ns. Under single-input change, a static-hazard-free two-level implementation is also free of dynamic hazards.

A functional hazard involves multiple changing inputs. For H=A+B, endpoints AB=01 and AB=10 both give H=1, but skew through AB=00 makes H=0 temporarily. Single-input consensus repair does not generally solve simultaneous changes.

Timing-safe design: elimination, settling and sampling are different fixes

For hazard-sensitive outputs, use overlapping K-map covers or consensus terms for the specified transitions. Hand-balanced delays are unreliable because process, voltage and temperature alter them. Analyse asynchronous controls explicitly.

Sampling after worst-case propagation may protect a synchronous register, but it neither removes internal switching nor makes an asynchronous control safe. Here the circuit is not guaranteed settled until 7 ns; sampling at 4 ns is unsafe.

Ignoring skew and jitter, let launch t_clk-q(max)=1.5 ns, combinational t_pd(max)=7 ns and setup time be 1 ns. Then T_clk >= 1.5+7+1=9.5 ns, so f_max <= 1/(9.5 ns), about 105.3 MHz. For t_clk-q(min)=0.5 ns, t_cd=2 ns and hold time 0.8 ns, 0.5+2=2.5 ns >= 0.8 ns; the zero-skew hold check passes.

Hazard and timing exam traps: classify before calculating

Four checks anchor the method. For AB+A'C, B=C=1 and falling A: the hazard is static-1; consensus is BC; the product gap is 5-3=2 ns; and A to Y has t_cd=2 ns, t_pd=7 ns. In the opposite transition, P rises at 3 ns before Q falls at 5 ns, so the terms overlap instead of leaving a gap.

Representative tasks ask you to classify an SOP or POS hazard, mark a missing K-map overlap, find a consensus term, trace a delay waveform, separate contamination from propagation delay, or calculate a clock bound. Use the GATE Test Series: Mocks & Topic-wise Tests for broader timed practice.

Hazards and timing: the short version and next step

Use this recall sequence:

1. Verify the ideal endpoint values.

2. Locate reconvergent paths and compare event arrival times.

3. Classify the unwanted pulse.

4. Add the K-map overlap or consensus term.

5. Verify both Boolean equivalence and timing behaviour.

Redraw F=AB+A'C from memory with B=C=1. Place P falling at 3 ns, Q rising at 5 ns, recover the 5 ns to 7 ns glitch, and explain why BC removes it without changing the truth table.

If you want Digital Logic arranged as a sequenced study path rather than isolated topics, GATE Guidance by Sanchit Sir is the honest next step. If this one concept is your only gap, repeat the waveform and K-map retrieval task first.