Write-through updates memory immediately, and most students can recite that much. Marks are lost after that point, on dirty bits, write-allocate, inclusive levels and coherence, where the answer turns on an exact event sequence. The 11 previous-year questions below come from GATE, UGC NET, ISRO, Coal India and CDAC CCAT. Attempt each one before reading its explanation, and use its practice link for a second pass later.
1. Cache coherence and write policy: propagation, allocation and dirty bits
Event or property | Write-through | Write-back |
|---|---|---|
Write hit | Cache and next level updated | Cache only updated |
Write miss | Often no-write-allocate | Often write-allocate |
Dirty bit | Normally unnecessary | Marks a newer cache copy |
Eviction traffic | No dirty write-back | Whole dirty block written |
Memory freshness | Current after write | May be stale until eviction |
These pairings are common, not required. Propagation and allocation are separate choices.
Initially, memory, P1 and P2 hold X = 10. A WT write by P1 makes its cache and memory 18; coherence invalidates or updates P2.
After a reset, a WB write makes P1 = 18, dirty = 1 and leaves memory at 10; coherence still handles P2. Eviction changes memory from 10 to 18 and ends the dirty obligation.
Snooping observes a shared broadcast medium. A directory records line holders and sends messages only to known sharers. Cache Memory: Mapping and Hit Ratio explains placement, which alone cannot solve coherence.
2. Write-through, write-back and dirty-bit fundamentals: Questions 1-3
Question 1, UGC NET June 2016
In _____ method, the word is written to the block in both the cache and main memory, in parallel.
A. Write through
B. Write back
C. Write protected
D. Direct mapping
Answer: A. Write-through updates cache and memory together. Write-back defers memory; protection and direct mapping concern access and placement.
Question 2, Coal India 2017
Which of the following statements related to Cache memory organization is FALSE?
A. In “write through” approach, main memory content is always invalid.
B. In “write back” approach, updates are made only in the cache and it minimizes memory writes.
C. Least Recently Used (LRU) replacement algorithm can be used in associative and set associative mappings.
D. For direct mapping, no replacement algorithm is needed.
Answer: A. Write-through keeps memory current, so A is false. B describes WB, C permits LRU among candidates, and D reflects direct mapping's single destination.
Question 3, GATE 2022
Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back cache and WT is a write through cache. Which of the following statements is/are FALSE?
A. Each cache block in WB and WT has a dirty bit.
B. Every write hit in WB leads to a data transfer from cache to main memory.
C. Eviction of a block from WT will not lead to data transfer from cache to main memory.
D. A read miss in WB will never lead to eviction of a dirty block from WB.
Answer: A, B and D. WB needs dirty tracking but its hit need not update memory, making A and B false. C is true; D is false because a read miss can evict a dirty victim.
3. Miss handling, allocation and eviction: Questions 4-6
In one 2-way set, LRU line A has cache 7, memory 5 and dirty = 1; MRU line B has value 4. A read miss for memory line C = 9 writes A's 7 to memory, evicts A, then installs C. Under WT, A cannot be dirty, so eviction writes nothing back.
Question 4, GATE 2021 Set 2
Assume a two-level inclusive cache hierarchy, L1 and L2, where L2 is the larger of the two. Consider the following statements.
S1: Read misses in a write through L1 cache do not result in writebacks of dirty lines to the L2
S2: Write allocate policy must be used in conjunction with write through caches and no-write allocate policy is used with writeback caches.
Which of the following statements is correct?
A. S1 is true and S2 is false
B. S1 is false and S2 is true
C. S1 is true and S2 is true
D. S1 is false and S2 is false
Answer: A. WT L1 has no dirty line to write back, so S1 is true. Allocation and propagation are independent, making S2 false despite the common pairings.
Question 5, GATE 2024 Set 1
Consider two set-associative cache memory architectures: WBC, which uses the write back policy, and WTC, which uses the write through policy. Both of them use the LRU (Least Recently Used) block replacement policy. The cache memory is connected to the main memory. Which of the following statements is/are TRUE?
A. A read miss in WBC never evicts a dirty block
B. A read miss in WTC never triggers a write back operation of a cache block to main memory
C. A write hit in WBC can modify the value of the dirty bit of a cache block
D. A write miss in WTC always writes the victim cache block to main memory before loading the missed block to the cache
Answer: B and C. A is false and B true: a WBC miss can evict a dirty victim, but a WTC victim is clean. C is true because a WBC hit can set dirty to 1; D wrongly requires write-back and allocation.
Question 6, CDAC CCAT 2017
Evict buffer is used in:
A. Write-through accesses
B. Write-back accesses
C. Both A and B
D. None of the above
Answer: B. An evict buffer drains a dirty victim while replacement continues. Only WB creates this deferred block transfer; WT victims are clean.
4. Inclusive cache levels and write policy: Question 7
Question 7, GATE 2008
For inclusion to hold between two cache levels L1 and L2 in a multi-level cache hierarchy, which of the following are necessary?
I. L1 must be a write-through cache
II. L2 must be a write-through cache
III. The associativity of L2 must be greater than that of L1
IV. The L2 cache must be at least as large as the L1 cache
A. IV only
B. I and IV only
C. I, III and IV only
D. I, II, III and IV
Answer: A. Inclusion requires L2 to represent every L1 line, so it must be at least as large. Neither write-through nor greater L2 associativity is necessary.
Memory Hierarchy and Virtual Memory Explained adds context: inclusion relates cache contents, while virtual memory handles translation and backing storage.
5. Snoopy and directory-based cache coherence: Questions 8-11
Question 8, UGC NET 2021
The cache coherence problem can be solved:
A. by having multiport memory
B. allow only nonshared data to be stored in cache
C. using a snoopy cache controller
D. using memory interleaving
Choose the correct answer from the options given below:
A. A and C only
B. B and C only
C. D and C only
D. B and D only
Answer: B. Nonshared-only caching avoids competing writable copies; snooping invalidates or updates shared copies. Multiport memory and interleaving improve access, but do not reconcile stale private caches.
Question 9, ISRO 2018
For a multi-processor architecture, In which protocol a write transaction is forwarded to only those processors that are known to possess a copy of newly altered cache line ?
A. Snoopy bus protocol
B. Cache coherency protocol
C. Directory based protocol
D. None of the above
Answer: C. A directory records sharers, so writes target only those processors. Snooping broadcasts for every controller, though only matching caches act.
Question 10, ISRO 2020
Which of the following is an efficient method of cache updating?
A. Snoopy writes
B. Write through
C. Write within
D. Buffered write
Answer: A. Snoopy controllers observe bus writes and update or invalidate matching copies. Write-through controls propagation, buffering hides latency, and “write within” is not a coherence method.
Question 11, UGC NET June 2025
Which of the following statements are true?
A. In the write-through policy, only the cache is updated.
B. In the write-back policy, both cache and main memory are updated.
C. Cache coherence problems exist in multiprocessors with private caches because of the need to share writable data.
D. Cache coherence problem can be solved by means of a hardware-only scheme.
Choose the correct answer from the options given below:
A. A, B Only
B. B, C Only
C. C, D Only
D. A, B, C Only
Answer: C. A and B reverse WT and WB behaviour. C identifies the shared writable-data problem; D is true because hardware protocols can maintain line consistency.
6. Cache coherence MCQ patterns and traps to revise
Questions 1-3 test propagation, 4-6 miss and eviction, 7 inclusion, and 8-11 coherence. Translate each option into an event sequence.
Write-through never updates the cache alone.
Write-back does not reach memory at the moment of the write.
A read miss can evict a dirty WB victim.
Write policy does not force allocation policy.
WT and snooping solve different problems.
Interleaving, multiport memory and mapping cannot repair stale private copies.
Recall the opening trace. After P1 changes X from 10 to 18, WT gives (P1=18, memory=18, dirty not needed, P2 invalidated or updated). WB gives (P1=18, memory=10, dirty=1, P2 invalidated or updated) until eviction writes 18.
7. Cache coherence and write policy: the short version and next step
WT updates the next level now.
WB waits for dirty eviction.
Allocation governs miss placement.
Dirty means cache is newer.
Snooping broadcasts.
Directories target known sharers.
Hide the answers and redo Questions 3, 4, 5, 7 and 11 with values and dirty-state transitions. Rebuild any unclear statement with the X: 10 to 18 trace.
Use GATE Guidance by Sanchit Sir for structured lessons, GATE Test Series for timed practice, and GATE CS Exam Preparation Courses & Test Series for the wider subject path.
