Cache Coherence and Write Policies: Write-Through, Write-Back and MESI Worked Step by Step

A cache write policy decides where a processor's new value is stored and when main memory changes. Cache coherence decides how several private caches avoid using different values for the same block. Students often merge these into one rule, then miscount memory traffic or MESI transitions. Write policy determines the outcome of the seven accesses, while MESI determines the two-core state transitions; both are relevant to GATE CS Exam Preparation.

Cache coherence and write policy solve two different problems

A write policy gives the rules for a write hit and a write miss. Coherence ensures that cores sharing an address eventually observe a valid, ordered value instead of continuing with stale private copies. Coherence concerns one memory location. Memory consistency is broader and constrains the observable order of operations across multiple locations.

Two plain-language invariants guide coherence. Write propagation means another core can eventually see a completed write. Write serialization means all cores agree on one order for writes to the same address.

Use a direct-mapped cache with two lines and one 4-byte word per line. Blocks A and C map to line 0, while B maps to line 1. Write buffers are ignored. Cache Write Policies and Multi-Level Cache Numericals combines policy traffic with AMAT and large reference counts. This two-line model holds AMAT and block size constant, exposing only hit policy, miss policy, mapping and initial state.

Write-through and write-back on a write hit

Suppose an already-cached word receives 4, then 9, then 12 before eviction. Write-through produces three memory writes. Write-back produces no memory write during those hits and one block write on dirty eviction. The byte count depends on the block size and bus-transfer size given in the question.

Write-through simplifies memory visibility and commonly uses a write buffer. The buffer may hide latency, but it does not erase transactions when traffic is being counted. Write-back can merge repeated stores, but main memory remains temporarily stale and a dirty eviction creates extra traffic.

Write-allocate and no-write-allocate on a write miss

Write-allocate first fetches the missed block into the cache, writes the requested word there, then follows the selected hit policy. No-write-allocate, also called write-around, sends the write to the lower level and leaves the missed block outside this cache.

Write-back commonly pairs with write-allocate because later writes can be combined in one dirty block. Write-through commonly pairs with no-write-allocate because a one-off store need not fetch a whole block. These are common choices, not laws. The combination stated in the problem always wins.

Placement is a separate decision. Direct, associative and set-associative mapping decide where an admitted block may sit. The write-miss policy decides whether the missed block is admitted at all. Use Cache Memory: Mapping and Hit Ratio for placement and hit-ratio calculations.

Cache write-policy worked example: trace seven accesses exactly

Start with an empty cache and memory values A=0, B=0 and C=0. Apply R(A), W(A)=10, W(A)=11, W(B)=20, W(B)=21, W(A)=12, W(C)=30. Count each one-word fill or write-back as one transfer.

For write-through plus no-write-allocate:

Final memory is A=12, B=21, C=30. Line 0 contains clean A=12 and line 1 is invalid. Traffic is 1 read + 6 writes = 7 word transfers.

For write-back plus write-allocate:

There are three reads, for A, B and C, plus one write-back of A. Traffic before a flush is 3 + 1 = 4 transfers. Memory is A=12, B=0, C=0, while the cache holds dirty C=30 in line 0 and dirty B=21 in line 1.

If a final flush is required, writing B and C adds two transfers. The total becomes 4 + 2 = 6, and memory becomes A=12, B=21, C=30. Without that flush, write-back saves 7 - 4 = 3 transfers here by merging repeated hits. A different block size, mapping or synchronization requirement changes the answer.

Cache coherence with MESI across two cores

MESI gives each cached block one state. Modified is the only valid copy and differs from memory. Exclusive is the only cached copy and is clean. Shared is one of multiple clean copies. Invalid cannot be used. With write-invalidate, a core must invalidate other shared copies before writing.

Within Multiprocessors in COA: Concepts, Amdahl's Law and Cache Coherence Worked Examples, MESI sits beside UMA, NUMA, interconnects and Amdahl's law. This seven-state sequence isolates one block's dirty-owner intervention, invalidation and eviction, the protocol actions most easily confused with write policy.

Let X begin as 0 in memory and remain absent from both private caches. Under the standard exam model where a modified owner supplies and writes back data on another core's read:

No step leaves two writable copies. P1 cannot read stale 0 after P0 owns modified 5, and both cores observe writes to X in the order 5 then 9. Directory-based coherence is another way to locate sharers, but its fields and message counts depend on the design.

Cache coherence and write-policy exam patterns and traps

Most questions ask you to trace cache and memory values, count fills and writes, or follow MESI states and invalidations for one block. Before calculating, write four labels above the trace: hit policy, miss policy, mapping and initial state.

A write-through estimate requires the store fraction and total reference count. Among 1,000 references, if 30% are stores, a basic write-through model produces 0.30 x 1,000 = 300 lower-level writes from stores, whether each store hits or misses. A write-back total cannot be obtained from a 90% cache hit rate alone because the number of dirty evictions is unknown.

Keep these corrections ready:

• Write-back is not the same as write-allocate.

• A write miss does not automatically cause a block fill.

• A clean eviction creates no write-back.

• Write-invalidate is not write-through.

• Coherence is not consistency.

• Main memory may be stale while a Modified line is valid.

KnowledgeGate has practice questions in this subtopic. Recheck the transfer counts once with a different mapping or final-flush requirement; changing one assumption exposes a memorised answer that was not actually derived.

Cache coherence and write policies: the short version and next step

For each access, apply the hit policy on hits and the miss policy on misses; write back dirty blocks on replacement and complete the coherence action before another writer proceeds.

1. On a hit, apply write-through or write-back.

2. On a miss, apply write-allocate or no-write-allocate.

3. On a dirty replacement, write the old block back.

4. With private multicore caches, complete the coherence action before another writer proceeds.

Memory remains B=0 after the write-back trace although the processor most recently wrote B=21. Line 1 still holds valid, dirty B=21. No eviction or flush has forced that value to memory.

If you want cache organisation taught alongside the rest of COA, GATE Guidance by Sanchit Sir provides the structured route. Before tracing any access, separate hit policy, miss policy, mapping and coherence into four labels.