Boolean Expressions in Digital Electronics: Laws, Canonical Forms and Worked Simplification

Students often recognise Boolean laws one at a time but lose marks when a question switches from an expression to a truth table, canonical notation, or a gate diagram. One function closes that gap: carry F(A,B,C) = A'B + AC through every representation and check at each step that its eight row outputs are unchanged. Digital Logic returns this chain in paper after paper, which is why it earns an early slot in any GATE preparation plan.

Boolean expressions: variables, operators and functions

A Boolean variable takes only 0 or 1. Here, A' means NOT A, adjacency or . means AND, and + means OR. Evaluate brackets first, then complements, AND operations, and finally OR operations.

An expression is a written formula. A Boolean function is the input-output behaviour that formula denotes, so different expressions can define the same function. Three inputs give 2^3 = 8 input rows and 2^(2^3) = 2^8 = 256 possible Boolean functions.

For the running function:

• At (A,B,C) = (0,1,0), F = 1.1 + 0.0 = 1.

• At (A,B,C) = (1,0,1), F = 0.0 + 1.1 = 1.

The dots show Boolean AND, not decimal multiplication.

Boolean laws that actually move an expression

Learn the laws by the job they perform:

• Identity and null: X+0=X, X.1=X, X+1=1, X.0=0. For example, A.1+0=A.

• Idempotent and complement: X+X=X, X.X=X, X+X'=1, X.X'=0. Thus BB+B'B=B.

• Absorption: X+XY=X and X(X+Y)=X. For example, A+AB=A.

• Distributive laws: X(Y+Z)=XY+XZ and X+YZ=(X+Y)(X+Z). Hence A+BC=(A+B)(A+C).

De Morgan's law must complement every term and swap AND with OR. For

G = [(A+B')C]':

G = (A+B')' + C' = A'(B')' + C' = A'B + C'.

Check (A,B,C)=(0,1,1): the original is [(0+0).1]'=0'=1, while the simplified form is 1.1+0=1. At (1,1,1), the original is [(1+0).1]'=1'=0, and the simplified form is 0.1+0=0.

Duality swaps + with ., and 0 with 1, while leaving variables and complements unchanged. The dual of X+0=X is X.1=X. This produces a companion identity; it is not the same as complementing an expression.

Truth table to canonical SOP and POS

Build the full table before reading the canonical forms:

The 1 rows give the canonical sum of products:

F = Σm(2,3,5,7) = A'BC' + A'BC + AB'C + ABC.

In a minterm, a 1 bit gives an uncomplemented literal and a 0 bit gives a complemented literal. Row 101 therefore gives AB'C.

The 0 rows give the canonical product of sums:

F = ΠM(0,1,4,6) = (A+B+C)(A+B+C')(A'+B+C)(A'+B'+C).

Maxterm polarity is reversed because the whole sum must be 0 on its row. For example, (A'+B+C') is 0 on row 101. That is the maxterm for index 5, although row 5 is not a zero row of this function.

Simplify the Boolean function and prove equivalence

Start from the canonical SOP and combine terms that differ in one literal:

A'BC' + A'BC + AB'C + ABC

= A'B(C'+C) + AC(B'+B)

= A'B.1 + AC.1

= A'B + AC.

The pairing is legal because C'+C=1 in the first pair and B'+B=1 in the second. A visual treatment of the same adjacency idea is available in the Boolean algebra and K-map minimisation guide.

An equivalent simplified POS is F=(A+B)(A'+C). The factor (A+B) is zero at indices 0,1; (A'+C) is zero at indices 4,6. Their product is therefore zero exactly at 0,1,4,6, matching the truth table.

Map the expression to gates and NAND gates

For the two-level circuit, one NOT gate makes A'. One AND gate receives A' and B, a second receives A and C, and one OR gate combines their outputs. This is a combinational circuit because its output depends only on present inputs. If output also depended on stored state, it would be sequential logic.

The same function needs four NAND gates:

1. A' = NAND(A,A)

2. N1 = NAND(A',B)

3. N2 = NAND(A,C)

4. F = NAND(N1,N2)

Trace (A,B,C)=(1,0,1): A'=0, N1=NAND(0,0)=1, N2=NAND(1,1)=0, and F=NAND(1,0)=1.

Common Boolean-expression traps

Complementing only visible symbols. The correct result is (AB+C)'=(A'+B')C', not A'B'+C'. At (1,1,0), the original and correct forms are 0; the wrong form is 1.

Mixing SOP and POS polarity. Use this check: a minterm must be 1 on its row, while a maxterm must be 0. For row 101, m5=AB'C=1 and M5=(A'+B+C')=0.

Reading OR as XOR or dropping precedence. At A=B=1, A+B=1, but A XOR B=A'B+AB'=0. At (A,B,C)=(0,1,0), both A+B.C and (A+B).C happen to give 0. The discriminating row is (1,0,0): A+B.C=1, while (A+B).C=0.

How GATE-style questions test the chain

Typical question forms ask you to evaluate an expression at a supplied vector, recover Σm or ΠM indices from a table, choose an equivalent expression, or trace a NAND or NOR realisation. These are different entry points into the same input-output function.

Try this compact check for H(A,B,C)=ΠM(0,2,5,7):

1. H(1,0,1)=0, because input 101 has index 5, which is in the maxterm list.

2. H'=Σm(0,2,5,7), because complementing H swaps its zero set into the 1 set of H'.

3. H=Σm(1,3,4,6), the four rows the maxterm list leaves out. Pairing them gives A'B'C + A'BC = A'C(B'+B) = A'C and AB'C' + ABC' = AC'(B'+B) = AC', so H = A'C + AC', which is A XOR C. Variable B never affects the output.

The short version and next practice step

• Fix notation and precedence.

• Make the truth table.

• Read 1 rows as minterms and 0 rows as maxterms.

• Simplify with named laws.

• Verify with outputs, not appearance.

• Map the reduced expression to gates.

Use a 25-minute loop: spend 5 minutes evaluating all eight rows, 7 minutes writing canonical SOP and POS, 8 minutes simplifying, and 5 minutes drawing and testing the circuit. If one representation fails, repeat that step instead of rereading the chapter.

For a structured subject plan, use GATE Guidance by Sanchit Sir. Then use the GATE Test Series to practise the same chain under test conditions.