Consider a pipeline with 5 stages and each stage with delay as shown below: IF…
Consider a pipeline with 5 stages and each stage with delay as shown below:
IF = 400ps
ID = 225ps
EX = 350ps
MEM = 450ps
WB = 300ps
To improve the performance of the above pipeline, if you have decided to break exactly 2 of the above stages into 2 shorter stages. What is the maximum speedup achieved with the new pipeline system to execute 100 instructions?
Answer: B. 1.26 — Answer: 1.26 Given stage delays (ps): IF = 400, ID = 225, EX = 350, MEM = 450, WB = 300. Number of instructions n = 100. Baseline pipeline: Number of cycles =…
- A.
1.52
- B.
1.26
- C.
2.46
- D.
3.24
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Correct answer: B
Answer: 1.26
Given stage delays (ps): IF = 400, ID = 225, EX = 350, MEM = 450, WB = 300. Number of instructions n = 100.
Baseline pipeline:
Number of cycles = number of stages + (n - 1) = 5 + 99 = 104.
Cycle time = maximum stage delay (no register delay given) = 450 ps.
Total time (baseline) = 104 × 450 ps = 46,800 ps.
After improvement (split exactly two stages):
Choose the two longest stages to split to minimize the new cycle time: MEM (450 ps) and IF (400 ps).
Splitting each in half gives: IF1 = 200 ps, IF2 = 200 ps; MEM1 = 225 ps, MEM2 = 225 ps. Other stages remain: ID = 225 ps, EX = 350 ps, WB = 300 ps.
New maximum stage delay = 350 ps (EX). New number of stages = 7.
Number of cycles = 7 + 99 = 106. Total time (improved) = 106 × 350 ps = 37,100 ps.
Speedup = baseline time / improved time = 46,800 / 37,100 ≈ 1.26.
Note: Assumed zero register overhead as none was provided. Rounding to two decimal places gives the reported value 1.26.