The 5 stages of processor fetch, decode, execute, memory, and write back have…
The 5 stages of processor fetch, decode, execute, memory, and write back have the following delays 110,240,160,220, and 305 ns respectively. Assume that when pipelining, each pipeline stage cost 15ns extra for the registers between pipeline stages. What is the throughput of the pipeline system (in million instructions per second)?
Answer: D. 3.12 MIPS — Answer: 3.12 MIPS is correct. Key idea: The pipeline cycle time is determined by the slowest stage plus the register overhead between pipeline stages. Stage…
- A.
5.15 MIPS
- B.
3.92 MIPS
- C.
2.55 MIPS
- D.
3.12 MIPS
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Correct answer: D
Answer: 3.12 MIPS is correct.
Key idea: The pipeline cycle time is determined by the slowest stage plus the register overhead between pipeline stages.
Stage delays: 110 ns, 240 ns, 160 ns, 220 ns, 305 ns.
Register overhead between stages: 15 ns (added to the slowest stage to get the cycle time).
Effective cycle time = max(stage delay) + register overhead = 305 ns + 15 ns = 320 ns.
Throughput = 1 / cycle time = 1 / 320 ns = 1 / (320 × 10^-9 s) = 3.125 × 10^6 instructions/s ≈ 3.12 MIPS.
Notes: The original solution referenced an option label and had a minor typographical/math presentation issue. This version removes label references and shows the full numeric calculation.