A processor P1 operating at 5GHz has a standard 6 RISC instruction pipeline…
A processor P1 operating at 5GHz has a standard 6 RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program that has 60% branch instructions, control hazards incur 3 cycles stall for every branch. A new version of the processor P2 operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for P1 and P2. If the BPU has a prediction accuracy of 90%, the speed up (rounded off to two decimal places) obtained by P2 over P1 in executing given program is _______________.
Answer: 2.37 — Given: base CPI = 1; 60% of instructions are branches; each branch causes 3 stall cycles if not eliminated; branch predictor accuracy = 90% (correct…
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Correct answer: 2.37
Given: base CPI = 1; 60% of instructions are branches; each branch causes 3 stall cycles if not eliminated; branch predictor accuracy = 90% (correct predictions eliminate stalls; wrong predictions incur the same stall). No other hazards.
CPI for the processor without a branch predictor: CPI = base CPI + fraction of branches × stall cycles per branch = 1 + 0.60 × 3 = 2.80
CPI for the processor with the branch predictor: only mispredicted branches cause stalls. Expected stall per instruction = fraction of branches × misprediction rate × stall cycles = 0.60 × 0.10 × 3 = 0.18. Therefore CPI = 1 + 0.18 = 1.18.
Speedup = old CPI / new CPI = 2.80 / 1.18 = 2.37288... Rounded to two decimal places: 2.37
Answer: The speedup obtained by the processor with the branch predictor is 2.37.