Consider an instruction with five stages without any branch prediction. Fetch…
Consider an instruction with five stages without any branch prediction. Fetch instruction (FI), decode instruction (DI), fetch operand (FO), execute instruction (EI) and write operand (WO). The stages delays for FI, DI, FO, EI, WO are 6ns, 9ns, 13ns, 10ns and 7ns respectively there are intermediate storage buffer after each stage and the delay of each buffer is 2nsec. A program consisting of 12 instructions. I1, I2, I3 --l12 is executed in this pipelined processor. I4 Instruction I is the only branch instruction and its branch target is l10 if branch is taken during the execution of the program the time (in nsec) needed to complete the program is ?
Answer: 210 — K = 5 stages -> 6ns, 9ns, 13ns, 10ns, 7ns Buffer delay = 2nsec tp = max(stage delay + buffer delay) = 13 + 2 Cycle Time = tp = 15nsec Without stalls ET in…
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Correct answer: 210
K = 5 stages -> 6ns, 9ns, 13ns, 10ns, 7ns
Buffer delay = 2nsec
tp = max(stage delay + buffer delay) = 13 + 2
Cycle Time = tp = 15nsec
Without stalls
ET in Pipeline = [K + (n - 1)] cycle = [5 + (7 - 1)] cycle = 11 cycles.
Total instructions: 12
11 12 13 14 I5 16 17 18 I9 I10 I11 I12
Out of 12 only 7 instructions in execution, n = 7.
Number of stalls = 3 (extra cycle) (no. of stage at which branch gets predicted(4,which is execution stage) - 1)
Total cycle = 11 + 3 = 14 cycle.
ETPIPE = 14 cycle [cycle time (tp) = 15 nsec] = 14 x 15 = 210nsec.