A CPU has a 32 KB direct mapped cache with 128 byte block size. Suppose A is a…

2017

A CPU has a 32 KB direct mapped cache with 128 byte block size. Suppose A is a 2 dimensional array of size 512×512 with elements that occupy 8 bytes each. Consider the code segment 

for (i =0; i < 512; i++) {
  for (j =0; j < 512; j++) {
    x += A[i][j];
  }
}

Assuming that array is stored in order A[0][0], A[0][1], A[0][2]……, the number of cache misses is

Answer: A. 16384 — The array A is stored in row-major order and accessed sequentially by the nested loops, meaning memory access aligns perfectly with storage layout without…

  1. A.

    16384

  2. B.

    512

  3. C.

    2048

  4. D.

    1024

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Correct answer: A

The array A is stored in row-major order and accessed sequentially by the nested loops, meaning memory access aligns perfectly with storage layout without conflict. Each cache block holds 16 elements (128 bytes divided by 8 bytes per element), so accessing the first element of a new block triggers a miss while subsequent elements hit. Total array elements are 262,144 (512×512), divided by 16 elements per block results in exactly 16,384 cache misses. Options B and C are incorrect because they underestimate the total number of unique blocks accessed, while D is too low as it ignores the full array size.

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